Angel Pons | 3bd1e3d | 2020-04-05 15:47:17 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 2 | |
Angel Pons | 72b8fd5 | 2021-09-28 10:28:38 +0200 | [diff] [blame] | 3 | #include <arch/io.h> |
Subrata Banik | c1d99c9 | 2017-12-14 16:28:45 +0530 | [diff] [blame] | 4 | #include <bootstate.h> |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 5 | #include <console/console.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 6 | #include <device/mmio.h> |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 7 | #include <device/device.h> |
Patrick Rudolph | e56189c | 2018-04-18 10:11:59 +0200 | [diff] [blame] | 8 | #include <device/pci_ops.h> |
Subrata Banik | 2153ea5 | 2017-11-22 15:38:19 +0530 | [diff] [blame] | 9 | #include <intelblocks/pmc.h> |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 10 | #include <intelblocks/pmclib.h> |
Subrata Banik | 2153ea5 | 2017-11-22 15:38:19 +0530 | [diff] [blame] | 11 | #include <intelblocks/rtc.h> |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 12 | #include <soc/pci_devs.h> |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 13 | #include <soc/pm.h> |
Subrata Banik | 2153ea5 | 2017-11-22 15:38:19 +0530 | [diff] [blame] | 14 | |
Elyes HAOUAS | c338507 | 2019-03-21 15:38:06 +0100 | [diff] [blame] | 15 | #include "chip.h" |
| 16 | |
Subrata Banik | 2153ea5 | 2017-11-22 15:38:19 +0530 | [diff] [blame] | 17 | /* Fill up PMC resource structure */ |
| 18 | int pmc_soc_get_resources(struct pmc_resource_config *cfg) |
| 19 | { |
| 20 | cfg->pwrmbase_offset = PWRMBASE; |
| 21 | cfg->pwrmbase_addr = PCH_PWRM_BASE_ADDRESS; |
| 22 | cfg->pwrmbase_size = PCH_PWRM_BASE_SIZE; |
| 23 | cfg->abase_offset = ABASE; |
| 24 | cfg->abase_addr = ACPI_BASE_ADDRESS; |
| 25 | cfg->abase_size = ACPI_BASE_SIZE; |
| 26 | |
| 27 | return 0; |
| 28 | } |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 29 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 30 | static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) |
| 31 | { |
| 32 | uint32_t reg; |
| 33 | uint8_t *pmcbase = pmc_mmio_regs(); |
| 34 | |
| 35 | printk(BIOS_DEBUG, "%sabling Deep S%c\n", |
| 36 | enable ? "En" : "Dis", sx + '0'); |
| 37 | reg = read32(pmcbase + offset); |
| 38 | if (enable) |
| 39 | reg |= mask; |
| 40 | else |
| 41 | reg &= ~mask; |
| 42 | write32(pmcbase + offset, reg); |
| 43 | } |
| 44 | |
Duncan Laurie | 1fe32d6 | 2017-04-10 21:02:13 -0700 | [diff] [blame] | 45 | static void config_deep_s5(int on_ac, int on_dc) |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 46 | { |
| 47 | /* Treat S4 the same as S5. */ |
Duncan Laurie | 1fe32d6 | 2017-04-10 21:02:13 -0700 | [diff] [blame] | 48 | config_deep_sX(S4_PWRGATE_POL, S4AC_GATE_SUS, 4, on_ac); |
| 49 | config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS, 4, on_dc); |
| 50 | config_deep_sX(S5_PWRGATE_POL, S5AC_GATE_SUS, 5, on_ac); |
| 51 | config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS, 5, on_dc); |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 52 | } |
| 53 | |
Duncan Laurie | 1fe32d6 | 2017-04-10 21:02:13 -0700 | [diff] [blame] | 54 | static void config_deep_s3(int on_ac, int on_dc) |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 55 | { |
Duncan Laurie | 1fe32d6 | 2017-04-10 21:02:13 -0700 | [diff] [blame] | 56 | config_deep_sX(S3_PWRGATE_POL, S3AC_GATE_SUS, 3, on_ac); |
| 57 | config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS, 3, on_dc); |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 58 | } |
| 59 | |
Duncan Laurie | edf1cb7 | 2015-07-24 15:37:13 -0700 | [diff] [blame] | 60 | static void config_deep_sx(uint32_t deepsx_config) |
| 61 | { |
| 62 | uint32_t reg; |
| 63 | uint8_t *pmcbase = pmc_mmio_regs(); |
| 64 | |
| 65 | reg = read32(pmcbase + DSX_CFG); |
| 66 | reg &= ~DSX_CFG_MASK; |
| 67 | reg |= deepsx_config; |
| 68 | write32(pmcbase + DSX_CFG, reg); |
| 69 | } |
| 70 | |
Subrata Banik | 2153ea5 | 2017-11-22 15:38:19 +0530 | [diff] [blame] | 71 | void pmc_soc_init(struct device *dev) |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 72 | { |
Kyösti Mälkki | 28dc7dc | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 73 | const config_t *config = config_of(dev); |
Angel Pons | 72b8fd5 | 2021-09-28 10:28:38 +0200 | [diff] [blame] | 74 | uint8_t *const pwrmbase = pmc_mmio_regs(); |
| 75 | uint32_t reg32; |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 76 | |
Subrata Banik | 2153ea5 | 2017-11-22 15:38:19 +0530 | [diff] [blame] | 77 | rtc_init(); |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 78 | |
Nico Huber | 04ce8fe | 2019-08-05 19:33:09 +0200 | [diff] [blame] | 79 | pmc_set_power_failure_state(true); |
| 80 | pmc_gpe_init(); |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 81 | |
Angel Pons | 72b8fd5 | 2021-09-28 10:28:38 +0200 | [diff] [blame] | 82 | /* SLP_S4=4s, SLP_S3=50ms, disable SLP_X stretching after SUS loss. */ |
| 83 | pci_update_config32(dev, GEN_PMCON_B, ~(S4MAW_MASK | SLP_S3_MIN_ASST_WDTH_MASK), |
| 84 | S4MAW_4S | SLP_S3_MIN_ASST_WDTH_50MS | DIS_SLP_X_STRCH_SUS_UP); |
| 85 | |
| 86 | /* Enable SCI and clear SLP requests. */ |
| 87 | reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); |
| 88 | reg32 &= ~SLP_TYP; |
| 89 | reg32 |= SCI_EN; |
| 90 | outl(reg32, ACPI_BASE_ADDRESS + PM1_CNT); |
| 91 | |
Subrata Banik | 2153ea5 | 2017-11-22 15:38:19 +0530 | [diff] [blame] | 92 | pmc_set_acpi_mode(); |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 93 | |
Duncan Laurie | 1fe32d6 | 2017-04-10 21:02:13 -0700 | [diff] [blame] | 94 | config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); |
| 95 | config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc); |
Duncan Laurie | edf1cb7 | 2015-07-24 15:37:13 -0700 | [diff] [blame] | 96 | config_deep_sx(config->deep_sx_config); |
Aaron Durbin | 6fd5bd2 | 2015-08-04 21:04:02 -0500 | [diff] [blame] | 97 | |
| 98 | /* Clear registers that contain write-1-to-clear bits. */ |
Angel Pons | 72b8fd5 | 2021-09-28 10:28:38 +0200 | [diff] [blame] | 99 | pci_or_config32(dev, GEN_PMCON_B, 0); |
| 100 | pci_or_config32(dev, GEN_PMCON_B, 0); |
| 101 | setbits32(pwrmbase + GBLRST_CAUSE0, 0); |
| 102 | setbits32(pwrmbase + GBLRST_CAUSE1, 0); |
Michael Niewöhner | 68bacc2 | 2021-09-24 23:57:37 +0200 | [diff] [blame] | 103 | |
| 104 | /* |
| 105 | * Disable ACPI PM timer based on Kconfig |
| 106 | * |
| 107 | * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. |
| 108 | * Disabling ACPI PM timer also switches off TCO. |
| 109 | */ |
| 110 | if (!CONFIG(USE_PM_ACPI_TIMER)) |
| 111 | setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS); |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 112 | } |
Subrata Banik | 7f4ec96 | 2017-12-19 10:27:45 +0530 | [diff] [blame] | 113 | |
Subrata Banik | c1d99c9 | 2017-12-14 16:28:45 +0530 | [diff] [blame] | 114 | static void pm1_enable_pwrbtn_smi(void *unused) |
| 115 | { |
| 116 | /* |
| 117 | * Enable power button SMI only before jumping to payload. This ensures |
| 118 | * that: |
| 119 | * 1. Power button SMI is enabled only after coreboot is done. |
| 120 | * 2. On resume path, power button SMI is not enabled and thus avoids |
| 121 | * any shutdowns because of power button presses due to power button |
| 122 | * press in resume path. |
| 123 | */ |
| 124 | pmc_update_pm1_enable(PWRBTN_EN); |
| 125 | } |
| 126 | |
| 127 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL); |
| 128 | |
Furquan Shaikh | 99d258a | 2018-10-05 11:04:01 -0700 | [diff] [blame] | 129 | /* |
| 130 | * Check if WAKE# pin is enabled based on DSX_EN_WAKE_PIN setting in |
| 131 | * deep_sx_config. If WAKE# pin is not enabled, then PCI Express Wake Disable |
| 132 | * bit needs to be set in PM1_EN to avoid unnecessary wakes caused by WAKE# |
| 133 | * pin. |
| 134 | */ |
| 135 | static void pm1_handle_wake_pin(void *unused) |
| 136 | { |
Kyösti Mälkki | d5f645c | 2019-09-28 00:20:27 +0300 | [diff] [blame] | 137 | const config_t *conf = config_of_soc(); |
Furquan Shaikh | 99d258a | 2018-10-05 11:04:01 -0700 | [diff] [blame] | 138 | |
| 139 | /* If WAKE# pin is enabled, bail out early. */ |
| 140 | if (conf->deep_sx_config & DSX_EN_WAKE_PIN) |
| 141 | return; |
| 142 | |
| 143 | pmc_update_pm1_enable(PCIEXPWAK_DIS); |
| 144 | } |
| 145 | |
| 146 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, pm1_handle_wake_pin, NULL); |
Arthur Heymans | 897d63a | 2023-02-01 11:10:00 +0100 | [diff] [blame] | 147 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, pm1_handle_wake_pin, NULL); |