blob: ca02a690dd8777caf7cf6d57a15f7e03e84cdceb [file] [log] [blame]
Angel Ponsae593872020-04-04 18:50:57 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Marc Jones24484842017-05-04 21:17:45 -06002
3// Use simple device model for this file even in ramstage
4#define __SIMPLE_DEVICE__
5
6#include <stdint.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +02007#include <device/pci_ops.h>
Marc Jones24484842017-05-04 21:17:45 -06008#include <device/pci_ehci.h>
9#include <device/pci_def.h>
Marshall Dawsonafaedc92018-10-12 10:22:33 -060010#include <soc/pci_devs.h>
Marc Jonesdfeb1c42017-08-07 19:08:24 -060011#include <soc/southbridge.h>
Arthur Heymans2c43bf72019-11-16 12:53:28 +010012#include <amdblocks/acpimmio.h>
Marc Jones24484842017-05-04 21:17:45 -060013
Marc Jones24484842017-05-04 21:17:45 -060014pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
15{
Marshall Dawson939bfcc2019-05-05 15:39:40 -060016 pm_io_write8(PM_USB_ENABLE, PM_USB_ALL_CONTROLLERS);
Marshall Dawsonafaedc92018-10-12 10:22:33 -060017 return SOC_EHCI1_DEV;
Marc Jones24484842017-05-04 21:17:45 -060018}
19
20void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
21{
Richard Spiegel6635b3d2018-08-24 16:48:20 -070022 u32 reg32, value;
Marc Jones24484842017-05-04 21:17:45 -060023
Richard Spiegel6635b3d2018-08-24 16:48:20 -070024 value = (port & 0x3) << DEBUG_PORT_SELECT_SHIFT;
25 value |= DEBUG_PORT_ENABLE;
26 reg32 = pci_read_config32(SOC_EHCI1_DEV, EHCI_HUB_CONFIG4);
27 reg32 &= ~DEBUG_PORT_MASK;
28 reg32 |= value;
29 pci_write_config32(SOC_EHCI1_DEV, EHCI_HUB_CONFIG4, reg32);
Marc Jones24484842017-05-04 21:17:45 -060030}