blob: 92a9b247cabdcfba85615e69876fc1d59fa74b8e [file] [log] [blame]
Patrick Georgi02363b52020-05-05 20:48:50 +02001/* This file is part of the coreboot project. */
Patrick Georgiac959032020-05-05 22:49:26 +02002/* SPDX-License-Identifier: GPL-2.0-only */
T Michael Turney7783c602019-10-09 07:04:54 -07003
4#include <symbols.h>
5#include <device/device.h>
6#include <soc/mmu.h>
7#include <soc/mmu_common.h>
8#include <soc/symbols.h>
Ravi Kumar Bokka6bbf8f22019-08-12 14:54:21 +05309#include <soc/aop.h>
T Michael Turney7783c602019-10-09 07:04:54 -070010
11static void soc_read_resources(struct device *dev)
12{
13 ram_resource(dev, 0, (uintptr_t)ddr_region->offset / KiB,
14 ddr_region->size / KiB);
Ravi Kumar Bokka6bbf8f22019-08-12 14:54:21 +053015 reserved_ram_resource(dev, 1, (uintptr_t)_dram_aop / KiB,
16 REGION_SIZE(dram_aop) / KiB);
17 reserved_ram_resource(dev, 2, (uintptr_t)_dram_soc / KiB,
T Michael Turney7783c602019-10-09 07:04:54 -070018 REGION_SIZE(dram_soc) / KiB);
19}
20
21static void soc_init(struct device *dev)
22{
Ravi Kumar Bokka6bbf8f22019-08-12 14:54:21 +053023 aop_fw_load_reset();
T Michael Turney7783c602019-10-09 07:04:54 -070024}
25
26static struct device_operations soc_ops = {
27 .read_resources = soc_read_resources,
28 .init = soc_init,
29};
30
31static void enable_soc_dev(struct device *dev)
32{
33 dev->ops = &soc_ops;
34}
35
36struct chip_operations soc_qualcomm_sc7180_ops = {
37 CHIP_NAME("SOC Qualcomm SC7180")
38 .enable_dev = enable_soc_dev,
39};