blob: 3b8a7998f34d0c7bce5217274bc11948401fdee2 [file] [log] [blame]
Patrick Georgi02363b52020-05-05 20:48:50 +02001/* This file is part of the coreboot project. */
Patrick Georgiac959032020-05-05 22:49:26 +02002/* SPDX-License-Identifier: GPL-2.0-only */
Nitheesh Sekar20e75872018-09-14 11:24:10 +05303
Nitheesh Sekar717050d2018-09-16 16:16:42 +05304#include <symbols.h>
Nitheesh Sekar20e75872018-09-14 11:24:10 +05305#include <device/device.h>
Nitheesh Sekar717050d2018-09-16 16:16:42 +05306#include <soc/mmu.h>
7#include <soc/symbols.h>
Nitheesh Sekar20e75872018-09-14 11:24:10 +05308
9static void soc_read_resources(struct device *dev)
10{
Nitheesh Sekar717050d2018-09-16 16:16:42 +053011 ram_resource(dev, 0, (uintptr_t)_dram / KiB, (1 * GiB) / KiB);
12 reserved_ram_resource(dev, 1, (uintptr_t)_dram_reserved / KiB,
13 REGION_SIZE(dram_reserved) / KiB);
Nitheesh Sekar20e75872018-09-14 11:24:10 +053014}
15
16static void soc_init(struct device *dev)
17{
18
19}
20
21static struct device_operations soc_ops = {
22 .read_resources = soc_read_resources,
23 .init = soc_init,
24};
25
26static void enable_soc_dev(struct device *dev)
27{
28 dev->ops = &soc_ops;
29}
30
31struct chip_operations soc_qualcomm_qcs405_ops = {
32 CHIP_NAME("SOC Qualcomm QCS405")
33 .enable_dev = enable_soc_dev,
34};