Patrick Georgi | 02363b5 | 2020-05-05 20:48:50 +0200 | [diff] [blame] | 1 | /* This file is part of the coreboot project. */ |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 2 | /* |
Uwe Hermann | 1410c2d | 2007-05-29 10:37:52 +0000 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; either version 2 of the License, or |
| 7 | * (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
Uwe Hermann | 1410c2d | 2007-05-29 10:37:52 +0000 | [diff] [blame] | 13 | */ |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 14 | |
Tobias Diedrich | e87c38e | 2010-11-27 09:40:16 +0000 | [diff] [blame] | 15 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 16 | #include <device/pci_ops.h> |
Tobias Diedrich | e87c38e | 2010-11-27 09:40:16 +0000 | [diff] [blame] | 17 | #include <console/console.h> |
Uwe Hermann | 9da69f8 | 2007-11-30 02:08:26 +0000 | [diff] [blame] | 18 | #include <stdint.h> |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 19 | #include <device/device.h> |
| 20 | #include <device/pci.h> |
| 21 | #include <device/pci_ids.h> |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 22 | #include <device/smbus.h> |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 23 | #include "chip.h" |
Stefan Reinauer | a14b468 | 2006-08-04 07:50:59 +0000 | [diff] [blame] | 24 | #include "i82371eb.h" |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 25 | |
Tobias Diedrich | e87c38e | 2010-11-27 09:40:16 +0000 | [diff] [blame] | 26 | static void pwrmgt_enable(struct device *dev) |
| 27 | { |
| 28 | struct southbridge_intel_i82371eb_config *sb = dev->chip_info; |
| 29 | u32 reg, gpo = sb->gpo; |
| 30 | |
| 31 | /* Sets the base address of power management ports. */ |
| 32 | pci_write_config16(dev, PMBA, DEFAULT_PMBASE | 1); |
| 33 | |
| 34 | /* Set Power Management IO Space Enable bit */ |
| 35 | u8 val = pci_read_config8(dev, PMREGMISC); |
| 36 | pci_write_config8(dev, PMREGMISC, val | 1); |
| 37 | |
| 38 | /* set global control: |
| 39 | * bit25 (lid_pol): 1=invert lid polarity |
| 40 | * bit24 (sm_freeze): 1=freeze idle and standby timers |
| 41 | * bit16 (end of smi): 0=disable smi assertion (cleared by hw) |
| 42 | * bits8-15,26: global standby timer inital count 127 * 4minutes |
| 43 | * bit2 (thrm_pol): 1=active low THRM# |
| 44 | * bit0 (smi_en): 1=disable smi generation upon smi event |
| 45 | */ |
| 46 | reg = (sb->lid_polarity<<25)| |
| 47 | (1<<24)| |
| 48 | (0xff<<8)| |
| 49 | (sb->thrm_polarity<<2); |
| 50 | outl(reg, DEFAULT_PMBASE + GLBCTL); |
| 51 | |
| 52 | /* set processor control: |
| 53 | * bit12 (stpclk_en): 1=enable stopping of host clk on lvl3 |
| 54 | * bit11 (sleep_en): 1=enable slp# assertion on lvl3 |
| 55 | * bit9 (cc_en): 1=enable clk control with lvl2 and lvl3 regs |
| 56 | */ |
| 57 | outl(0, DEFAULT_PMBASE + PCNTRL); |
| 58 | |
| 59 | /* disable smi event enables */ |
| 60 | outw(0, DEFAULT_PMBASE + GLBEN); |
| 61 | outl(0, DEFAULT_PMBASE + DEVCTL); |
| 62 | |
| 63 | /* set default gpo value. |
| 64 | * power-on default is 0x7fffbfffh */ |
| 65 | if (gpo) { |
| 66 | /* only 8bit access allowed */ |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 67 | outb(gpo & 0xff, DEFAULT_PMBASE + GPO0); |
Tobias Diedrich | e87c38e | 2010-11-27 09:40:16 +0000 | [diff] [blame] | 68 | outb((gpo >> 8) & 0xff, DEFAULT_PMBASE + GPO1); |
| 69 | outb((gpo >> 16) & 0xff, DEFAULT_PMBASE + GPO2); |
| 70 | outb((gpo >> 24) & 0xff, DEFAULT_PMBASE + GPO3); |
| 71 | } else { |
| 72 | printk(BIOS_SPEW, |
| 73 | "%s: gpo default missing in devicetree.cb!\n", __func__); |
| 74 | } |
| 75 | |
| 76 | /* Clear status events. */ |
| 77 | outw(0xffff, DEFAULT_PMBASE + PMSTS); |
| 78 | outw(0xffff, DEFAULT_PMBASE + GPSTS); |
| 79 | outw(0xffff, DEFAULT_PMBASE + GLBSTS); |
| 80 | outl(0xffffffff, DEFAULT_PMBASE + DEVSTS); |
| 81 | |
Tobias Diedrich | 4e22a3b | 2010-12-13 22:39:46 +0100 | [diff] [blame] | 82 | /* set PMCNTRL default */ |
Tobias Diedrich | e87c38e | 2010-11-27 09:40:16 +0000 | [diff] [blame] | 83 | outw(SUS_TYP_S0|SCI_EN, DEFAULT_PMBASE + PMCNTRL); |
| 84 | } |
| 85 | |
| 86 | static void pwrmgt_read_resources(struct device *dev) |
| 87 | { |
| 88 | struct resource *res; |
| 89 | |
| 90 | pci_dev_read_resources(dev); |
| 91 | |
| 92 | res = new_resource(dev, 1); |
| 93 | res->base = DEFAULT_PMBASE; |
| 94 | res->size = 0x0040; |
| 95 | res->limit = 0xffff; |
| 96 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | |
| 97 | IORESOURCE_RESERVE; |
| 98 | |
| 99 | res = new_resource(dev, 2); |
| 100 | res->base = SMBUS_IO_BASE; |
| 101 | res->size = 0x0010; |
| 102 | res->limit = 0xffff; |
| 103 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | |
| 104 | IORESOURCE_RESERVE; |
| 105 | } |
| 106 | |
| 107 | |
Uwe Hermann | 9da69f8 | 2007-11-30 02:08:26 +0000 | [diff] [blame] | 108 | static const struct smbus_bus_operations lops_smbus_bus = { |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 109 | }; |
| 110 | |
Uwe Hermann | 9da69f8 | 2007-11-30 02:08:26 +0000 | [diff] [blame] | 111 | static const struct device_operations smbus_ops = { |
Tobias Diedrich | e87c38e | 2010-11-27 09:40:16 +0000 | [diff] [blame] | 112 | .read_resources = pwrmgt_read_resources, |
Uwe Hermann | 1410c2d | 2007-05-29 10:37:52 +0000 | [diff] [blame] | 113 | .set_resources = pci_dev_set_resources, |
| 114 | .enable_resources = pci_dev_enable_resources, |
Kyösti Mälkki | d0e212c | 2015-02-26 20:47:47 +0200 | [diff] [blame] | 115 | .scan_bus = scan_smbus, |
Tobias Diedrich | e87c38e | 2010-11-27 09:40:16 +0000 | [diff] [blame] | 116 | .enable = pwrmgt_enable, |
Uwe Hermann | 56a9125 | 2007-06-03 16:57:27 +0000 | [diff] [blame] | 117 | .ops_pci = 0, /* No subsystem IDs on 82371EB! */ |
Uwe Hermann | 1410c2d | 2007-05-29 10:37:52 +0000 | [diff] [blame] | 118 | .ops_smbus_bus = &lops_smbus_bus, |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 119 | }; |
| 120 | |
Uwe Hermann | 9da69f8 | 2007-11-30 02:08:26 +0000 | [diff] [blame] | 121 | /* Note: There's no SMBus on 82371FB/SB/MX and 82437MX. */ |
| 122 | |
| 123 | /* Intel 82371AB/EB/MB */ |
Stefan Reinauer | f1cf1f7 | 2007-10-24 09:08:58 +0000 | [diff] [blame] | 124 | static const struct pci_driver smbus_driver __pci_driver = { |
Uwe Hermann | 1410c2d | 2007-05-29 10:37:52 +0000 | [diff] [blame] | 125 | .ops = &smbus_ops, |
| 126 | .vendor = PCI_VENDOR_ID_INTEL, |
Uwe Hermann | 447aafe | 2007-11-29 01:44:43 +0000 | [diff] [blame] | 127 | .device = PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI, |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 128 | }; |