After finding the missing bit poweroff works now.
I cleaned up the patch and moved most of the dsdt.dsl and
acpi_tables.c into the southbrige/northbridge directory.
Updated patch should fix abuild error and incorporates suggestions
on irc by uwe (thanks for the comments).
Thanks to Idwer Vollering <vidwer@gmail.com> for the original patch.
Tested:
Linux (poweroff, powerbutton event)
XP (poweroff, powerbutton event)
Abuild-tested
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6127 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/southbridge/intel/i82371eb/i82371eb_smbus.c b/src/southbridge/intel/i82371eb/i82371eb_smbus.c
index 3072b6c..4dfd2f4 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_smbus.c
+++ b/src/southbridge/intel/i82371eb/i82371eb_smbus.c
@@ -2,6 +2,9 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2010 Keith Hui <buurin@gmail.com>
+ * Copyright (C) 2010 Idwer Vollering <vidwer@gmail.com>
+ * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -18,6 +21,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <arch/io.h>
+#include <console/console.h>
#include <stdint.h>
#include <device/device.h>
#include <device/pci.h>
@@ -26,17 +31,98 @@
#include "i82371eb.h"
#include "i82371eb_smbus.h"
-/* TODO: Needed later? */
+static void pwrmgt_enable(struct device *dev)
+{
+ struct southbridge_intel_i82371eb_config *sb = dev->chip_info;
+ u32 reg, gpo = sb->gpo;
+
+ /* Sets the base address of power management ports. */
+ pci_write_config16(dev, PMBA, DEFAULT_PMBASE | 1);
+
+ /* Set Power Management IO Space Enable bit */
+ u8 val = pci_read_config8(dev, PMREGMISC);
+ pci_write_config8(dev, PMREGMISC, val | 1);
+
+ /* set global control:
+ * bit25 (lid_pol): 1=invert lid polarity
+ * bit24 (sm_freeze): 1=freeze idle and standby timers
+ * bit16 (end of smi): 0=disable smi assertion (cleared by hw)
+ * bits8-15,26: global standby timer inital count 127 * 4minutes
+ * bit2 (thrm_pol): 1=active low THRM#
+ * bit0 (smi_en): 1=disable smi generation upon smi event
+ */
+ reg = (sb->lid_polarity<<25)|
+ (1<<24)|
+ (0xff<<8)|
+ (sb->thrm_polarity<<2);
+ outl(reg, DEFAULT_PMBASE + GLBCTL);
+
+ /* set processor control:
+ * bit12 (stpclk_en): 1=enable stopping of host clk on lvl3
+ * bit11 (sleep_en): 1=enable slp# assertion on lvl3
+ * bit9 (cc_en): 1=enable clk control with lvl2 and lvl3 regs
+ */
+ outl(0, DEFAULT_PMBASE + PCNTRL);
+
+ /* disable smi event enables */
+ outw(0, DEFAULT_PMBASE + GLBEN);
+ outl(0, DEFAULT_PMBASE + DEVCTL);
+
+ /* set default gpo value.
+ * power-on default is 0x7fffbfffh */
+ if (gpo) {
+ /* only 8bit access allowed */
+ outb( gpo & 0xff, DEFAULT_PMBASE + GPO0);
+ outb((gpo >> 8) & 0xff, DEFAULT_PMBASE + GPO1);
+ outb((gpo >> 16) & 0xff, DEFAULT_PMBASE + GPO2);
+ outb((gpo >> 24) & 0xff, DEFAULT_PMBASE + GPO3);
+ } else {
+ printk(BIOS_SPEW,
+ "%s: gpo default missing in devicetree.cb!\n", __func__);
+ }
+
+ /* Clear status events. */
+ outw(0xffff, DEFAULT_PMBASE + PMSTS);
+ outw(0xffff, DEFAULT_PMBASE + GPSTS);
+ outw(0xffff, DEFAULT_PMBASE + GLBSTS);
+ outl(0xffffffff, DEFAULT_PMBASE + DEVSTS);
+
+ /* set pmcntrl default */
+ outw(SUS_TYP_S0|SCI_EN, DEFAULT_PMBASE + PMCNTRL);
+}
+
+static void pwrmgt_read_resources(struct device *dev)
+{
+ struct resource *res;
+
+ pci_dev_read_resources(dev);
+
+ res = new_resource(dev, 1);
+ res->base = DEFAULT_PMBASE;
+ res->size = 0x0040;
+ res->limit = 0xffff;
+ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED |
+ IORESOURCE_RESERVE;
+
+ res = new_resource(dev, 2);
+ res->base = SMBUS_IO_BASE;
+ res->size = 0x0010;
+ res->limit = 0xffff;
+ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED |
+ IORESOURCE_RESERVE;
+}
+
+
static const struct smbus_bus_operations lops_smbus_bus = {
};
static const struct device_operations smbus_ops = {
- .read_resources = pci_dev_read_resources,
+ .read_resources = pwrmgt_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = 0,
.scan_bus = scan_static_bus,
- .enable = 0,
+ .enable = pwrmgt_enable,
.ops_pci = 0, /* No subsystem IDs on 82371EB! */
.ops_smbus_bus = &lops_smbus_bus,
};