| Ritul Guru | 286c2f6 | 2021-02-05 23:53:28 +0530 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
| 3 | if BOARD_AMD_BILBY |
| 4 | |
| 5 | config BOARD_SPECIFIC_OPTIONS |
| 6 | def_bool y |
| Ritul Guru | 286c2f6 | 2021-02-05 23:53:28 +0530 | [diff] [blame] | 7 | select SOC_AMD_PICASSO |
| 8 | select BOARD_ROMSIZE_KB_16384 |
| 9 | select AZALIA_PLUGIN_SUPPORT |
| 10 | select HAVE_ACPI_RESUME |
| 11 | select DRIVERS_UART_ACPI |
| 12 | select AMD_SOC_CONSOLE_UART if !AMD_LPC_DEBUG_CARD |
| 13 | |
| 14 | config FMDFILE |
| 15 | string |
| 16 | default "src/mainboard/amd/bilby/board.fmd" |
| 17 | |
| 18 | config AMD_LPC_DEBUG_CARD |
| 19 | bool "Enable LPC-Serial debug card on the debug header" |
| 20 | default n |
| 21 | select BILBY_LPC |
| 22 | select SUPERIO_SMSC_SIO1036 |
| 23 | help |
| 24 | AMD's debug card contains an SMSC SIO1036 device which provides an |
| 25 | I/O-mapped UART in the system. This is mutually exclusive with |
| 26 | AMD_SOC_CONSOLE_UART which selects the SoC's integrated memory-mapped |
| 27 | UART for coreboot console output. |
| 28 | |
| 29 | choice |
| 30 | prompt "SMSC/Microchip 1036 SuperIO config address" |
| 31 | depends on SUPERIO_SMSC_SIO1036 |
| 32 | default BILBY_SMSC_SIO1036_BASE_164E |
| 33 | |
| 34 | config BILBY_SMSC_SIO1036_BASE_4E |
| 35 | bool "0x4e/0x4d base address" |
| 36 | |
| 37 | config BILBY_SMSC_SIO1036_BASE_164E |
| 38 | bool "0x164e/0x164d base address" |
| 39 | |
| 40 | endchoice |
| 41 | |
| 42 | config SUPERIO_ADDR_BASE |
| 43 | hex |
| 44 | default 0x4e if BILBY_SMSC_SIO1036_BASE_4E |
| 45 | default 0x164e if BILBY_SMSC_SIO1036_BASE_164E |
| 46 | |
| 47 | config CBFS_SIZE |
| Ritul Guru | 3e945f1 | 2021-02-19 08:36:27 +0530 | [diff] [blame] | 48 | default 0xfef000 # Maximum size for the Bilby FMAP |
| Ritul Guru | 286c2f6 | 2021-02-05 23:53:28 +0530 | [diff] [blame] | 49 | |
| 50 | config MAINBOARD_DIR |
| 51 | string |
| 52 | default "amd/bilby" |
| 53 | |
| 54 | config MAINBOARD_PART_NUMBER |
| 55 | string |
| 56 | default "BILBY" |
| 57 | |
| Ritul Guru | 286c2f6 | 2021-02-05 23:53:28 +0530 | [diff] [blame] | 58 | config ONBOARD_VGA_IS_PRIMARY |
| 59 | bool |
| 60 | default y |
| 61 | |
| Ritul Guru | 286c2f6 | 2021-02-05 23:53:28 +0530 | [diff] [blame] | 62 | if !AMD_LPC_DEBUG_CARD |
| 63 | choice |
| 64 | prompt "State of IOMux for LPC/eMMC signals" |
| 65 | default BILBY_IOMUX_USE_EMMC |
| 66 | help |
| 67 | Bilby is designed to use either LPC or eMMC signals. Use this |
| 68 | selection to determine which are configured for this image. |
| 69 | |
| 70 | config BILBY_IOMUX_USE_LPC |
| 71 | bool "LPC signals" |
| 72 | |
| 73 | config BILBY_IOMUX_USE_EMMC |
| 74 | bool "eMMC signals" |
| 75 | |
| 76 | endchoice |
| 77 | endif # !AMD_LPC_DEBUG_CARD |
| 78 | |
| 79 | config BILBY_LPC |
| 80 | bool |
| 81 | default y if BILBY_IOMUX_USE_LPC |
| 82 | help |
| 83 | Picasso's LPC bus signals are MUXed with some of the EMMC signals. |
| 84 | Select this option if LPC signals are required. |
| 85 | |
| 86 | #TODO: remove this hack to not break graphics in combination with SeaBIOS |
| 87 | config VGA_BIOS_DGPU_ID |
| 88 | string |
| 89 | default "1002,15d8" |
| 90 | help |
| 91 | The default VGA BIOS PCI vendor/device ID should be set to the |
| 92 | result of the map_oprom_vendev() function in northbridge.c. |
| 93 | |
| 94 | config VGA_BIOS_DGPU_FILE |
| 95 | string |
| Ritul Guru | 7dccf47 | 2021-04-09 15:14:03 +0530 | [diff] [blame] | 96 | default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin" |
| Ritul Guru | 286c2f6 | 2021-02-05 23:53:28 +0530 | [diff] [blame] | 97 | |
| 98 | config EFS_SPI_READ_MODE |
| 99 | int |
| 100 | default 0 if EM100 |
| 101 | default 3 |
| 102 | |
| 103 | config EFS_SPI_SPEED |
| 104 | int |
| 105 | default 3 if EM100 |
| 106 | default 0 |
| 107 | |
| 108 | config EFS_SPI_MICRON_FLAG |
| 109 | int |
| 110 | default 0 |
| 111 | |
| 112 | endif # BOARD_AMD_BILBY |