| jinkun.hong | ac490b8 | 2014-06-22 20:40:39 -0700 | [diff] [blame^] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright 2014 Rockchip Inc. |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
| 15 | ## You should have received a copy of the GNU General Public License |
| 16 | ## along with this program; if not, write to the Free Software |
| 17 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | ## |
| 19 | |
| 20 | config SOC_ROCKCHIP_RK3288 |
| 21 | bool |
| 22 | default n |
| 23 | select ARCH_BOOTBLOCK_ARMV7 |
| 24 | select ARCH_VERSTAGE_ARMV7 |
| 25 | select ARCH_ROMSTAGE_ARMV7 |
| 26 | select ARCH_RAMSTAGE_ARMV7 |
| 27 | select CPU_HAS_BOOTBLOCK_INIT |
| 28 | select HAVE_MONOTONIC_TIMER |
| 29 | select HAVE_UART_MEMORY_MAPPED |
| 30 | select HAVE_UART_SPECIAL |
| 31 | select BOOTBLOCK_CONSOLE |
| 32 | select DYNAMIC_CBMEM |
| 33 | |
| 34 | if SOC_ROCKCHIP_RK3288 |
| 35 | |
| 36 | config BOOTBLOCK_CPU_INIT |
| 37 | string |
| 38 | default "soc/rockchip/rk3288/bootblock.c" |
| 39 | |
| 40 | # ROM image layout. |
| 41 | # |
| 42 | # 0x00000 Combined bootblock and ID Block |
| 43 | # 0x08000 Master CBFS header. |
| 44 | # 0x18000 Free for CBFS data. |
| 45 | # |
| 46 | # iRAM (96k) layout. |
| 47 | # (Note: The BootROM will jump to 0xff704004 after loading bootblock, |
| 48 | # so the bootblock loading address must be at 0xff704004.) |
| 49 | # |
| 50 | # 0xFF70_0000 TTB (16KB). |
| 51 | # 0xFF70_4004 Bootblock (max 16KB-4B). |
| 52 | # 0xFF70_8000 ROM stage (max 40KB). |
| 53 | # 0xFF71_2000 STACK (4KB). |
| 54 | # 0xFF71_3000 CBFS mapping cache (20K) |
| 55 | # 0xFF71_7FFF End of iRAM. |
| 56 | |
| 57 | config SYS_SDRAM_BASE |
| 58 | hex "SDRAM base address" |
| 59 | default 0x00000000 |
| 60 | |
| 61 | config STACK_TOP |
| 62 | hex "STACK TOP" |
| 63 | default 0xff713000 |
| 64 | |
| 65 | config STACK_BOTTOM |
| 66 | hex "STACK BOTTOM" |
| 67 | default 0xff712000 |
| 68 | |
| 69 | config BOOTBLOCK_BASE |
| 70 | hex |
| 71 | default 0xff704004 |
| 72 | |
| 73 | config ROMSTAGE_BASE |
| 74 | hex "ROM STAGE BASE" |
| 75 | default 0xff708000 |
| 76 | |
| 77 | config RAMSTAGE_BASE |
| 78 | hex "RAMSTAGE BASE" |
| 79 | default 0x00200000 |
| 80 | |
| 81 | config BOOTBLOCK_ROM_OFFSET |
| 82 | hex |
| 83 | default 0x0 |
| 84 | |
| 85 | config CBFS_HEADER_ROM_OFFSET |
| 86 | hex |
| 87 | default 0x0008000 |
| 88 | |
| 89 | config CBFS_ROM_OFFSET |
| 90 | hex |
| 91 | default 0x0018000 |
| 92 | |
| 93 | config CBFS_SRAM_CACHE_ADDRESS |
| 94 | hex "sram memory address to put CBFS cache data" |
| 95 | default 0xff713000 |
| 96 | |
| 97 | config CBFS_SRAM_CACHE_SIZE |
| 98 | hex "size of CBFS cache data" |
| 99 | default 0x00005000 |
| 100 | |
| 101 | config CBFS_DRAM_CACHE_ADDRESS |
| 102 | hex "dram memory address to put CBFS cache data" |
| 103 | default 0x01000000 |
| 104 | |
| 105 | config CBFS_DRAM_CACHE_SIZE |
| 106 | hex "size of CBFS cache data" |
| 107 | default 0x00100000 |
| 108 | |
| 109 | config TTB_BUFFER |
| 110 | hex "memory address of the TTB buffer" |
| 111 | default 0xff700000 |
| 112 | |
| 113 | config CONSOLE_SERIAL_UART_ADDRESS |
| 114 | hex |
| 115 | depends on CONSOLE_SERIAL_UART |
| 116 | default 0xFF690000 |
| 117 | |
| 118 | endif |