Jianjun Wang | ac1410d | 2021-07-14 15:39:40 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <commonlib/stdlib.h> |
| 4 | #include <console/console.h> |
| 5 | #include <device/mmio.h> |
| 6 | #include <device/resource.h> |
| 7 | #include <delay.h> |
| 8 | #include <soc/addressmap.h> |
| 9 | #include <soc/gpio.h> |
| 10 | #include <soc/pcie.h> |
| 11 | #include <soc/pcie_common.h> |
| 12 | #include <stdlib.h> |
| 13 | #include <string.h> |
| 14 | |
| 15 | #define PCIE_REG_BASE_PORT0 0x112f0000 |
| 16 | #define PCIE_RST_CTRL_REG (PCIE_REG_BASE_PORT0 + 0x148) |
| 17 | #define PCIE_MAC_RSTB BIT(0) |
| 18 | #define PCIE_PHY_RSTB BIT(1) |
| 19 | #define PCIE_BRG_RSTB BIT(2) |
| 20 | #define PCIE_PE_RSTB BIT(3) |
| 21 | |
| 22 | |
| 23 | /* MMIO range (64MB): 0x20000000 ~ 0x24000000 */ |
| 24 | /* Some devices still need io ranges, reserve 16MB for compatibility */ |
| 25 | static const struct mtk_pcie_mmio_res pcie_mmio_res_io = { |
| 26 | .cpu_addr = 0x20000000, |
| 27 | .pci_addr = 0x20000000, |
| 28 | .size = 16 * MiB, |
| 29 | .type = IORESOURCE_IO, |
| 30 | }; |
| 31 | |
| 32 | static const struct mtk_pcie_mmio_res pcie_mmio_res_mem = { |
| 33 | .cpu_addr = 0x21000000, |
| 34 | .pci_addr = 0x21000000, |
| 35 | .size = 48 * MiB, |
| 36 | .type = IORESOURCE_MEM, |
| 37 | }; |
| 38 | |
| 39 | struct pad_func { |
| 40 | gpio_t gpio; |
| 41 | u8 func; |
| 42 | }; |
| 43 | |
| 44 | #define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func} |
| 45 | |
| 46 | static const struct pad_func pcie_pins[2][3] = { |
| 47 | { |
| 48 | PAD_FUNC(PCIE_WAKE_N, WAKEN), |
| 49 | PAD_FUNC(PCIE_PERESET_N, PERSTN), |
| 50 | PAD_FUNC(PCIE_CLKREQ_N, CLKREQN), |
| 51 | }, |
| 52 | { |
| 53 | PAD_FUNC(CMMCLK0, PERSTN_1), |
| 54 | PAD_FUNC(CMMCLK1, CLKREQN_1), |
| 55 | PAD_FUNC(CMMCLK2, WAKEN_1), |
| 56 | }, |
| 57 | }; |
| 58 | |
| 59 | static void mtk_pcie_set_pinmux(uint8_t port) |
| 60 | { |
| 61 | const struct pad_func *pins = pcie_pins[port]; |
| 62 | size_t i; |
| 63 | |
| 64 | for (i = 0; i < ARRAY_SIZE(pcie_pins[port]); i++) { |
| 65 | gpio_set_mode(pins[i].gpio, pins[i].func); |
| 66 | gpio_set_pull(pins[i].gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP); |
| 67 | } |
| 68 | } |
| 69 | |
| 70 | static void mtk_pcie_reset(uintptr_t reg, bool enable) |
| 71 | { |
| 72 | uint32_t val; |
| 73 | |
| 74 | val = read32p(reg); |
| 75 | |
| 76 | if (enable) |
| 77 | val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | |
| 78 | PCIE_PE_RSTB; |
| 79 | else |
| 80 | val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | |
| 81 | PCIE_PE_RSTB); |
| 82 | |
| 83 | write32p(reg, val); |
| 84 | } |
| 85 | |
| 86 | void mtk_pcie_pre_init(void) |
| 87 | { |
| 88 | mtk_pcie_set_pinmux(0); |
| 89 | |
| 90 | /* Assert all reset signals at early stage */ |
| 91 | mtk_pcie_reset(PCIE_RST_CTRL_REG, true); |
| 92 | } |
| 93 | |
| 94 | void mtk_pcie_get_hw_info(struct mtk_pcie_controller *ctrl) |
| 95 | { |
| 96 | ctrl->base = PCIE_REG_BASE_PORT0; |
| 97 | ctrl->mmio_res_io = &pcie_mmio_res_io; |
| 98 | ctrl->mmio_res_mem = &pcie_mmio_res_mem; |
| 99 | ctrl->reset = &mtk_pcie_reset; |
| 100 | } |