| Matt DeVillier | abd561b | 2023-08-04 13:07:56 -0500 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #ifndef VARIANT_H |
| 4 | #define VARIANT_H |
| 5 | |
| 6 | #include <stdint.h> |
| 7 | |
| 8 | /* |
| 9 | * RAM_ID[2:0] are on GPIO_SSUS[39:37] |
| 10 | * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz |
| 11 | * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz |
| 12 | * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz |
| 13 | * 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz |
| 14 | * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz |
| 15 | * 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz |
| 16 | */ |
| 17 | |
| 18 | static const uint32_t dual_channel_config = |
| 19 | (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); |
| 20 | |
| 21 | #define SPD_SIZE 256 |
| 22 | #define GPIO_SSUS_37_PAD 57 |
| 23 | #define GPIO_SSUS_38_PAD 50 |
| 24 | #define GPIO_SSUS_39_PAD 58 |
| 25 | |
| 26 | #endif |