Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 secunet Security Networks AG |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 15 | */ |
| 16 | |
Kyösti Mälkki | ef84401 | 2013-06-25 23:17:43 +0300 | [diff] [blame] | 17 | // Use simple device model for this file even in ramstage |
| 18 | #define __SIMPLE_DEVICE__ |
| 19 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 20 | #include <stdint.h> |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 21 | #include <arch/cpu.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 22 | #include <device/pci_ops.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 23 | #include <device/pci_def.h> |
| 24 | #include <console/console.h> |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 25 | #include <cpu/intel/romstage.h> |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 26 | #include <cpu/x86/mtrr.h> |
Kyösti Mälkki | dcb688e | 2013-09-04 01:11:16 +0300 | [diff] [blame] | 27 | #include <cbmem.h> |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 28 | #include <program_loading.h> |
Kyösti Mälkki | aba8fb1 | 2019-08-02 06:11:28 +0300 | [diff] [blame^] | 29 | #include <stage_cache.h> |
Arthur Heymans | 009518e | 2018-11-27 14:06:21 +0100 | [diff] [blame] | 30 | #include <cpu/intel/smm/gen1/smi.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 31 | #include "gm45.h" |
| 32 | |
Arthur Heymans | eeaf9e4 | 2016-11-12 20:13:07 +0100 | [diff] [blame] | 33 | /* |
| 34 | * Decodes used Graphics Mode Select (GMS) to kilobytes. |
| 35 | * The options for 1M, 4M, 8M and 16M preallocated igd memory are |
| 36 | * undocumented but are verified to work. |
| 37 | */ |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 38 | u32 decode_igd_memory_size(const u32 gms) |
| 39 | { |
Arthur Heymans | eeaf9e4 | 2016-11-12 20:13:07 +0100 | [diff] [blame] | 40 | static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256, |
| 41 | 96, 160, 224, 352 }; |
| 42 | |
Jacob Garber | f74f6cb | 2019-04-08 17:54:35 -0600 | [diff] [blame] | 43 | if (gms >= ARRAY_SIZE(ggc2uma)) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 44 | die("Bad Graphics Mode Select (GMS) setting.\n"); |
Arthur Heymans | eeaf9e4 | 2016-11-12 20:13:07 +0100 | [diff] [blame] | 45 | |
| 46 | return ggc2uma[gms] << 10; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 47 | } |
| 48 | |
| 49 | /** Decodes used Graphics Stolen Memory (GSM) to kilobytes. */ |
| 50 | u32 decode_igd_gtt_size(const u32 gsm) |
| 51 | { |
| 52 | switch (gsm) { |
| 53 | case 0: |
| 54 | return 0 << 10; |
| 55 | case 1: |
| 56 | return 1 << 10; |
| 57 | case 3: |
| 58 | case 9: |
| 59 | return 2 << 10; |
| 60 | case 10: |
| 61 | return 3 << 10; |
| 62 | case 11: |
| 63 | return 4 << 10; |
| 64 | default: |
| 65 | die("Bad Graphics Stolen Memory (GSM) setting.\n"); |
| 66 | return 0; |
| 67 | } |
| 68 | } |
| 69 | |
Arthur Heymans | 8b76605 | 2018-01-24 23:25:13 +0100 | [diff] [blame] | 70 | /* Decodes TSEG region size to kilobytes. */ |
| 71 | u32 decode_tseg_size(u8 esmramc) |
| 72 | { |
| 73 | if (!(esmramc & 1)) |
| 74 | return 0; |
| 75 | switch ((esmramc >> 1) & 3) { |
| 76 | case 0: |
| 77 | return 1 << 10; |
| 78 | case 1: |
| 79 | return 2 << 10; |
| 80 | case 2: |
| 81 | return 8 << 10; |
| 82 | case 3: |
| 83 | default: |
| 84 | die("Bad TSEG setting.\n"); |
| 85 | } |
| 86 | } |
| 87 | |
Arthur Heymans | 009518e | 2018-11-27 14:06:21 +0100 | [diff] [blame] | 88 | u32 northbridge_get_tseg_base(void) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 89 | { |
Kyösti Mälkki | 3f9a62e | 2013-06-20 20:25:21 +0300 | [diff] [blame] | 90 | const pci_devfn_t dev = PCI_DEV(0, 0, 0); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 91 | |
| 92 | u32 tor; |
| 93 | |
| 94 | /* Top of Lower Usable DRAM */ |
| 95 | tor = (pci_read_config16(dev, D0F0_TOLUD) & 0xfff0) << 16; |
| 96 | |
| 97 | /* Graphics memory comes next */ |
| 98 | const u32 ggc = pci_read_config16(dev, D0F0_GGC); |
Arthur Heymans | 8b76605 | 2018-01-24 23:25:13 +0100 | [diff] [blame] | 99 | const u8 esmramc = pci_read_config8(dev, D0F0_ESMRAMC); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 100 | if (!(ggc & 2)) { |
| 101 | /* Graphics memory */ |
| 102 | tor -= decode_igd_memory_size((ggc >> 4) & 0xf) << 10; |
| 103 | /* GTT Graphics Stolen Memory Size (GGMS) */ |
| 104 | tor -= decode_igd_gtt_size((ggc >> 8) & 0xf) << 10; |
| 105 | } |
Arthur Heymans | 8b76605 | 2018-01-24 23:25:13 +0100 | [diff] [blame] | 106 | /* TSEG size */ |
| 107 | tor -= decode_tseg_size(esmramc) << 10; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 108 | return tor; |
| 109 | } |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 110 | |
Arthur Heymans | 009518e | 2018-11-27 14:06:21 +0100 | [diff] [blame] | 111 | u32 northbridge_get_tseg_size(void) |
| 112 | { |
| 113 | const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC); |
| 114 | return decode_tseg_size(esmramc) << 10; |
| 115 | } |
| 116 | |
Kyösti Mälkki | 811932a | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 117 | /* Depending of UMA and TSEG configuration, TSEG might start at any |
Elyes HAOUAS | 64f6b71 | 2018-08-07 12:16:56 +0200 | [diff] [blame] | 118 | * 1 MiB alignment. As this may cause very greedy MTRR setup, push |
Kyösti Mälkki | 811932a | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 119 | * CBMEM top downwards to 4 MiB boundary. |
| 120 | */ |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 121 | void *cbmem_top(void) |
| 122 | { |
Arthur Heymans | 009518e | 2018-11-27 14:06:21 +0100 | [diff] [blame] | 123 | uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); |
Kyösti Mälkki | 811932a | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 124 | return (void *) top_of_ram; |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 125 | } |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 126 | |
Kyösti Mälkki | aba8fb1 | 2019-08-02 06:11:28 +0300 | [diff] [blame^] | 127 | void stage_cache_external_region(void **base, size_t *size) |
| 128 | { |
| 129 | /* |
| 130 | * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. |
| 131 | * The top of RAM is defined to be the TSEG base address. |
| 132 | */ |
| 133 | *size = CONFIG_SMM_RESERVED_SIZE; |
| 134 | *base = (void *)(northbridge_get_tseg_base() |
| 135 | + CONFIG_SMM_RESERVED_SIZE); |
| 136 | } |
| 137 | |
Arthur Heymans | 3a4edb6 | 2018-06-03 12:42:10 +0200 | [diff] [blame] | 138 | /* platform_enter_postcar() determines the stack to use after |
| 139 | * cache-as-ram is torn down as well as the MTRR settings to use, |
| 140 | * and continues execution in postcar stage. */ |
| 141 | void platform_enter_postcar(void) |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 142 | { |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 143 | struct postcar_frame pcf; |
| 144 | uintptr_t top_of_ram; |
| 145 | |
Kyösti Mälkki | 6e2d0c1 | 2019-06-28 10:08:51 +0300 | [diff] [blame] | 146 | if (postcar_frame_init(&pcf, 0)) |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 147 | die("Unable to initialize postcar frame.\n"); |
| 148 | |
| 149 | /* Cache the ROM as WP just below 4GiB. */ |
Nico Huber | 089b908 | 2018-05-27 14:37:32 +0200 | [diff] [blame] | 150 | postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 151 | |
| 152 | /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ |
| 153 | postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); |
| 154 | |
Arthur Heymans | 009518e | 2018-11-27 14:06:21 +0100 | [diff] [blame] | 155 | /* Cache 8 MiB region below the top of ram and 2 MiB above top of |
Arthur Heymans | aade90e | 2018-01-25 00:33:45 +0100 | [diff] [blame] | 156 | * ram to cover both cbmem as the TSEG region. |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 157 | */ |
| 158 | top_of_ram = (uintptr_t)cbmem_top(); |
Arthur Heymans | 009518e | 2018-11-27 14:06:21 +0100 | [diff] [blame] | 159 | postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, |
| 160 | MTRR_TYPE_WRBACK); |
| 161 | postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), |
| 162 | northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 163 | |
Arthur Heymans | 3a4edb6 | 2018-06-03 12:42:10 +0200 | [diff] [blame] | 164 | run_postcar_phase(&pcf); |
| 165 | |
| 166 | /* We do not return here. */ |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 167 | } |