| Naresh G Solanki | ab5d690 | 2016-10-15 18:13:55 +0530 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2013 Google Inc. |
| 6 | * Copyright (C) 2016 Intel Corporation. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #include <arch/acpi.h> |
| 19 | #include <console/console.h> |
| 20 | #include <device/device.h> |
| 21 | #include <gpio.h> |
| 22 | #include <stdlib.h> |
| 23 | #include <string.h> |
| 24 | #include <soc/nhlt.h> |
| 25 | #include <vendorcode/google/chromeos/chromeos.h> |
| 26 | #include "ec.h" |
| 27 | #include "gpio.h" |
| 28 | |
| 29 | static const char *oem_id_maxim = "INTEL"; |
| 30 | static const char *oem_table_id_maxim = "SCRDMAX"; |
| 31 | |
| 32 | static void mainboard_init(device_t dev) |
| 33 | { |
| 34 | if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) |
| 35 | mainboard_ec_init(); |
| 36 | } |
| 37 | |
| 38 | static uint8_t select_audio_codec(void) |
| 39 | { |
| 40 | int audio_db_sel = gpio_get(AUDIO_DB_ID); |
| 41 | |
| 42 | return audio_db_sel; |
| 43 | } |
| 44 | |
| 45 | static unsigned long mainboard_write_acpi_tables( |
| 46 | device_t device, unsigned long current, acpi_rsdp_t *rsdp) |
| 47 | { |
| 48 | uintptr_t start_addr; |
| 49 | uintptr_t end_addr; |
| 50 | struct nhlt *nhlt; |
| 51 | const char *oem_id = NULL; |
| 52 | const char *oem_table_id = NULL; |
| 53 | |
| 54 | start_addr = current; |
| 55 | |
| 56 | nhlt = nhlt_init(); |
| 57 | |
| 58 | if (nhlt == NULL) |
| 59 | return start_addr; |
| 60 | |
| 61 | /* 2 Channel DMIC array. */ |
| 62 | if (nhlt_soc_add_dmic_array(nhlt, 2)) |
| 63 | printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); |
| 64 | |
| 65 | |
| 66 | /* 4 Channel DMIC array. */ |
| 67 | if (nhlt_soc_add_dmic_array(nhlt, 4)) |
| 68 | printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n"); |
| 69 | |
| 70 | if (select_audio_codec()) { |
| 71 | /* ADI Smart Amps for left and right. */ |
| 72 | if (nhlt_soc_add_ssm4567(nhlt, AUDIO_LINK_SSP0)) |
| 73 | printk(BIOS_ERR, "Couldn't add ssm4567.\n"); |
| 74 | } else { |
| 75 | /* MAXIM Smart Amps for left and right. */ |
| 76 | if (nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP0)) |
| 77 | printk(BIOS_ERR, "Couldn't add max98357.\n"); |
| 78 | |
| 79 | oem_id = oem_id_maxim; |
| 80 | oem_table_id = oem_table_id_maxim; |
| 81 | } |
| 82 | |
| 83 | /* NAU88l25 Headset codec. */ |
| 84 | if (nhlt_soc_add_nau88l25(nhlt, AUDIO_LINK_SSP1)) |
| 85 | printk(BIOS_ERR, "Couldn't add headset codec.\n"); |
| 86 | |
| 87 | end_addr = nhlt_soc_serialize_oem_overrides(nhlt, start_addr, |
| 88 | oem_id, oem_table_id); |
| 89 | |
| 90 | if (end_addr != start_addr) |
| 91 | acpi_add_table(rsdp, (void *)start_addr); |
| 92 | |
| 93 | return end_addr; |
| 94 | } |
| 95 | |
| 96 | /* |
| 97 | * mainboard_enable is executed as first thing after |
| 98 | * enumerate_buses(). |
| 99 | */ |
| 100 | static void mainboard_enable(device_t dev) |
| 101 | { |
| 102 | dev->ops->init = mainboard_init; |
| 103 | dev->ops->write_acpi_tables = mainboard_write_acpi_tables; |
| 104 | dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; |
| 105 | } |
| 106 | |
| 107 | struct chip_operations mainboard_ops = { |
| 108 | .enable_dev = mainboard_enable, |
| 109 | }; |