Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 2 | |
Vladimir Serbinenko | 4695705 | 2013-11-26 01:16:20 +0100 | [diff] [blame] | 3 | #ifndef SOUTHBRIDGE_INTEL_IBEXPEAK_CHIP_H |
| 4 | #define SOUTHBRIDGE_INTEL_IBEXPEAK_CHIP_H |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 5 | |
Keith Hui | ab4de83 | 2024-04-13 16:04:14 -0400 | [diff] [blame^] | 6 | #include <southbridge/intel/common/spi.h> |
| 7 | #include <types.h> |
| 8 | #include "pch.h" |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 9 | |
Keith Hui | ab4de83 | 2024-04-13 16:04:14 -0400 | [diff] [blame^] | 10 | struct southbridge_intel_ibexpeak_config { |
| 11 | /** |
| 12 | * GPI Routing configuration |
| 13 | * |
| 14 | * Only the lower two bits have a meaning: |
| 15 | * 00: No effect |
| 16 | * 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) |
| 17 | * 10: SCI (if corresponding GPIO_EN bit is also set) |
| 18 | * 11: reserved |
| 19 | */ |
| 20 | uint8_t gpi0_routing; |
| 21 | uint8_t gpi1_routing; |
| 22 | uint8_t gpi2_routing; |
| 23 | uint8_t gpi3_routing; |
| 24 | uint8_t gpi4_routing; |
| 25 | uint8_t gpi5_routing; |
| 26 | uint8_t gpi6_routing; |
| 27 | uint8_t gpi7_routing; |
| 28 | uint8_t gpi8_routing; |
| 29 | uint8_t gpi9_routing; |
| 30 | uint8_t gpi10_routing; |
| 31 | uint8_t gpi11_routing; |
| 32 | uint8_t gpi12_routing; |
| 33 | uint8_t gpi13_routing; |
| 34 | uint8_t gpi14_routing; |
| 35 | uint8_t gpi15_routing; |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 36 | |
Keith Hui | ab4de83 | 2024-04-13 16:04:14 -0400 | [diff] [blame^] | 37 | uint32_t gpe0_en; |
| 38 | uint16_t alt_gp_smi_en; |
| 39 | |
| 40 | /* IDE configuration */ |
| 41 | uint8_t sata_port_map; |
| 42 | uint32_t sata_port0_gen3_tx; |
| 43 | uint32_t sata_port1_gen3_tx; |
| 44 | |
| 45 | /** |
| 46 | * SATA Interface Speed Support Configuration |
| 47 | * |
| 48 | * Only the lower two bits have a meaning: |
| 49 | * 00 - No effect (leave as chip default) |
| 50 | * 01 - 1.5 Gb/s maximum speed |
| 51 | * 10 - 3.0 Gb/s maximum speed |
| 52 | * 11 - 6.0 Gb/s maximum speed |
| 53 | */ |
| 54 | uint8_t sata_interface_speed_support; |
| 55 | |
| 56 | uint32_t gen1_dec; |
| 57 | uint32_t gen2_dec; |
| 58 | uint32_t gen3_dec; |
| 59 | uint32_t gen4_dec; |
| 60 | |
| 61 | /* Enable linear PCIe Root Port function numbers starting at zero */ |
| 62 | bool pcie_port_coalesce; |
| 63 | |
| 64 | /* Override PCIe ASPM */ |
| 65 | uint8_t pcie_aspm[8]; |
| 66 | |
| 67 | int docking_supported; |
| 68 | |
| 69 | bool pcie_hotplug_map[8]; |
| 70 | |
| 71 | /* These USB3 fields, copied from bd82x6x, don't apply here, |
| 72 | * as Ibex Peak doesn't have USB3. */ |
| 73 | uint32_t xhci_switchable_ports; |
| 74 | uint32_t superspeed_capable_ports; |
| 75 | uint32_t xhci_overcurrent_mapping; |
| 76 | |
| 77 | uint32_t spi_uvscc; |
| 78 | uint32_t spi_lvscc; |
| 79 | struct intel_swseq_spi_config spi; |
| 80 | }; |
| 81 | |
| 82 | #endif /* SOUTHBRIDGE_INTEL_IBEXPEAK_CHIP_H */ |