Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 Google Inc |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <stdint.h> |
| 18 | #include <stdlib.h> |
| 19 | #include <console/console.h> |
| 20 | #include <arch/io.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 21 | #include <device/pci_def.h> |
Duncan Laurie | f4d3623 | 2012-06-23 16:37:45 -0700 | [diff] [blame] | 22 | #include <elog.h> |
Vladimir Serbinenko | c845b43 | 2014-09-05 03:37:44 +0200 | [diff] [blame] | 23 | #include <cbmem.h> |
Vladimir Serbinenko | 5fc04d1 | 2014-08-03 01:59:38 +0200 | [diff] [blame] | 24 | #include <pc80/mc146818rtc.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 25 | #include "sandybridge.h" |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 26 | |
| 27 | static void sandybridge_setup_bars(void) |
| 28 | { |
| 29 | /* Setting up Southbridge. In the northbridge code. */ |
| 30 | printk(BIOS_DEBUG, "Setting up static southbridge registers..."); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 31 | pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 32 | |
| 33 | pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); |
| 34 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ |
| 35 | |
| 36 | printk(BIOS_DEBUG, " done.\n"); |
| 37 | |
| 38 | printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); |
| 39 | RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ |
| 40 | outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ |
| 41 | printk(BIOS_DEBUG, " done.\n"); |
| 42 | |
| 43 | printk(BIOS_DEBUG, "Setting up static northbridge registers..."); |
| 44 | /* Set up all hardcoded northbridge BARs */ |
| 45 | pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); |
| 46 | pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 47 | pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); |
| 48 | pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+(uintptr_t)DEFAULT_MCHBAR) >> 32); |
| 49 | pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); |
| 50 | pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+(uintptr_t)DEFAULT_DMIBAR) >> 32); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 51 | |
| 52 | /* Set C0000-FFFFF to access RAM on both reads and writes */ |
| 53 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); |
| 54 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); |
| 55 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33); |
| 56 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33); |
| 57 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33); |
| 58 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); |
| 59 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); |
| 60 | |
Duncan Laurie | f4d3623 | 2012-06-23 16:37:45 -0700 | [diff] [blame] | 61 | #if CONFIG_ELOG_BOOT_COUNT |
| 62 | /* Increment Boot Counter for non-S3 resume */ |
| 63 | if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && |
| 64 | ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) |
| 65 | boot_count_increment(); |
| 66 | #endif |
| 67 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 68 | printk(BIOS_DEBUG, " done.\n"); |
Duncan Laurie | 9c4c6ab | 2012-06-29 15:38:02 -0700 | [diff] [blame] | 69 | |
| 70 | #if CONFIG_ELOG_BOOT_COUNT |
| 71 | /* Increment Boot Counter except when resuming from S3 */ |
| 72 | if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && |
| 73 | ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) |
| 74 | return; |
| 75 | boot_count_increment(); |
| 76 | #endif |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 77 | } |
| 78 | |
| 79 | static void sandybridge_setup_graphics(void) |
| 80 | { |
| 81 | u32 reg32; |
| 82 | u16 reg16; |
| 83 | u8 reg8; |
Vladimir Serbinenko | 5fc04d1 | 2014-08-03 01:59:38 +0200 | [diff] [blame] | 84 | u8 gfxsize; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 85 | |
| 86 | reg16 = pci_read_config16(PCI_DEV(0,2,0), PCI_DEVICE_ID); |
| 87 | switch (reg16) { |
| 88 | case 0x0102: /* GT1 Desktop */ |
| 89 | case 0x0106: /* GT1 Mobile */ |
| 90 | case 0x010a: /* GT1 Server */ |
| 91 | case 0x0112: /* GT2 Desktop */ |
| 92 | case 0x0116: /* GT2 Mobile */ |
| 93 | case 0x0122: /* GT2 Desktop >=1.3GHz */ |
| 94 | case 0x0126: /* GT2 Mobile >=1.3GHz */ |
Patrick Rudolph | 03a88d3 | 2015-07-05 13:29:41 +0200 | [diff] [blame] | 95 | case 0x0152: /* IvyBridge */ |
Stefan Reinauer | 816e9d1 | 2013-01-14 10:25:43 -0800 | [diff] [blame] | 96 | case 0x0156: /* IvyBridge */ |
Damien Zammit | a10bde9 | 2014-10-23 13:29:32 +1100 | [diff] [blame] | 97 | case 0x0162: /* IvyBridge */ |
Stefan Reinauer | 816e9d1 | 2013-01-14 10:25:43 -0800 | [diff] [blame] | 98 | case 0x0166: /* IvyBridge */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 99 | break; |
| 100 | default: |
| 101 | printk(BIOS_DEBUG, "Graphics not supported by this CPU/chipset.\n"); |
| 102 | return; |
| 103 | } |
| 104 | |
| 105 | printk(BIOS_DEBUG, "Initializing Graphics...\n"); |
| 106 | |
Vladimir Serbinenko | 5fc04d1 | 2014-08-03 01:59:38 +0200 | [diff] [blame] | 107 | if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { |
| 108 | /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */ |
| 109 | gfxsize = 0; |
| 110 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 111 | reg16 = pci_read_config16(PCI_DEV(0,0,0), GGC); |
| 112 | reg16 &= ~0x00f8; |
Vladimir Serbinenko | 5fc04d1 | 2014-08-03 01:59:38 +0200 | [diff] [blame] | 113 | reg16 |= (gfxsize + 1) << 3; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 114 | /* Program GTT memory by setting GGC[9:8] = 2MB */ |
| 115 | reg16 &= ~0x0300; |
| 116 | reg16 |= 2 << 8; |
| 117 | /* Enable VGA decode */ |
| 118 | reg16 &= ~0x0002; |
| 119 | pci_write_config16(PCI_DEV(0,0,0), GGC, reg16); |
| 120 | |
| 121 | /* Enable 256MB aperture */ |
| 122 | reg8 = pci_read_config8(PCI_DEV(0, 2, 0), MSAC); |
| 123 | reg8 &= ~0x06; |
| 124 | reg8 |= 0x02; |
| 125 | pci_write_config8(PCI_DEV(0, 2, 0), MSAC, reg8); |
| 126 | |
| 127 | /* Erratum workarounds */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 128 | reg32 = MCHBAR32(0x5f00); |
| 129 | reg32 |= (1 << 9)|(1 << 10); |
| 130 | MCHBAR32(0x5f00) = reg32; |
| 131 | |
| 132 | /* Enable SA Clock Gating */ |
| 133 | reg32 = MCHBAR32(0x5f00); |
| 134 | MCHBAR32(0x5f00) = reg32 | 1; |
| 135 | |
| 136 | /* GPU RC6 workaround for sighting 366252 */ |
| 137 | reg32 = MCHBAR32(0x5d14); |
| 138 | reg32 |= (1 << 31); |
| 139 | MCHBAR32(0x5d14) = reg32; |
| 140 | |
| 141 | /* VLW */ |
| 142 | reg32 = MCHBAR32(0x6120); |
| 143 | reg32 &= ~(1 << 0); |
| 144 | MCHBAR32(0x6120) = reg32; |
| 145 | |
| 146 | reg32 = MCHBAR32(0x5418); |
| 147 | reg32 |= (1 << 4) | (1 << 5); |
| 148 | MCHBAR32(0x5418) = reg32; |
| 149 | } |
| 150 | |
Patrick Rudolph | e4f9d5c | 2015-10-15 11:09:15 +0200 | [diff] [blame] | 151 | static void start_peg_link_training(void) |
| 152 | { |
| 153 | u32 tmp; |
| 154 | u32 deven; |
| 155 | |
| 156 | /* PEG on IvyBridge+ needs a special startup sequence. |
| 157 | * As the MRC has its own initialization code skip it. */ |
| 158 | if (((pci_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID) & |
| 159 | BASE_REV_MASK) != BASE_REV_IVB) || |
| 160 | IS_ENABLED(CONFIG_HAVE_MRC)) |
| 161 | return; |
| 162 | |
| 163 | deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); |
| 164 | |
| 165 | if (deven & DEVEN_PEG10) { |
| 166 | tmp = pci_read_config32(PCI_DEV(0, 1, 0), 0xC24) & ~(1 << 16); |
| 167 | pci_write_config32(PCI_DEV(0, 1, 0), 0xC24, tmp | (1 << 5)); |
| 168 | } |
| 169 | |
| 170 | if (deven & DEVEN_PEG11) { |
| 171 | tmp = pci_read_config32(PCI_DEV(0, 1, 1), 0xC24) & ~(1 << 16); |
| 172 | pci_write_config32(PCI_DEV(0, 1, 1), 0xC24, tmp | (1 << 5)); |
| 173 | } |
| 174 | |
| 175 | if (deven & DEVEN_PEG12) { |
| 176 | tmp = pci_read_config32(PCI_DEV(0, 1, 2), 0xC24) & ~(1 << 16); |
| 177 | pci_write_config32(PCI_DEV(0, 1, 2), 0xC24, tmp | (1 << 5)); |
| 178 | } |
| 179 | |
| 180 | if (deven & DEVEN_PEG60) { |
| 181 | tmp = pci_read_config32(PCI_DEV(0, 6, 0), 0xC24) & ~(1 << 16); |
| 182 | pci_write_config32(PCI_DEV(0, 6, 0), 0xC24, tmp | (1 << 5)); |
| 183 | } |
| 184 | } |
| 185 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 186 | void sandybridge_early_initialization(int chipset_type) |
| 187 | { |
| 188 | u32 capid0_a; |
Patrick Rudolph | 2a510a7 | 2015-07-28 07:51:10 +0200 | [diff] [blame] | 189 | u32 deven; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 190 | u8 reg8; |
| 191 | |
| 192 | /* Device ID Override Enable should be done very early */ |
| 193 | capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4); |
| 194 | if (capid0_a & (1 << 10)) { |
| 195 | reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf3); |
| 196 | reg8 &= ~7; /* Clear 2:0 */ |
| 197 | |
| 198 | if (chipset_type == SANDYBRIDGE_MOBILE) |
| 199 | reg8 |= 1; /* Set bit 0 */ |
| 200 | |
| 201 | pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8); |
| 202 | } |
| 203 | |
| 204 | /* Setup all BARs required for early PCIe and raminit */ |
| 205 | sandybridge_setup_bars(); |
| 206 | |
Nico Huber | bb9469c | 2015-10-21 11:49:23 +0200 | [diff] [blame] | 207 | /* Setup IOMMU BARs */ |
| 208 | sandybridge_init_iommu(); |
| 209 | |
Patrick Rudolph | 2a510a7 | 2015-07-28 07:51:10 +0200 | [diff] [blame] | 210 | /* Device Enable, don't touch PEG bits */ |
| 211 | deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN) | DEVEN_IGD; |
| 212 | pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, deven); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 213 | |
| 214 | sandybridge_setup_graphics(); |
Patrick Rudolph | e4f9d5c | 2015-10-15 11:09:15 +0200 | [diff] [blame] | 215 | |
| 216 | /* Write magic value to start PEG link training. |
| 217 | * This should be done in PCI device enumeration, but |
| 218 | * the PCIe specification requires to wait at least 100msec |
| 219 | * after reset for devices to come up. |
| 220 | * As we don't want to increase boot time, enable it early and |
| 221 | * assume the PEG is up as soon as PCI enumeration starts. |
| 222 | * TODO: use time stamps to ensure the timings are met */ |
| 223 | start_peg_link_training(); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 224 | } |
Vladimir Serbinenko | c845b43 | 2014-09-05 03:37:44 +0200 | [diff] [blame] | 225 | |
| 226 | void northbridge_romstage_finalize(int s3resume) |
| 227 | { |
| 228 | MCHBAR16(SSKPD) = 0xCAFE; |
| 229 | |
| 230 | #if CONFIG_HAVE_ACPI_RESUME |
| 231 | /* If there is no high memory area, we didn't boot before, so |
| 232 | * this is not a resume. In that case we just create the cbmem toc. |
| 233 | */ |
| 234 | |
| 235 | *(u32 *)CBMEM_BOOT_MODE = 0; |
| 236 | *(u32 *)CBMEM_RESUME_BACKUP = 0; |
| 237 | |
| 238 | if (s3resume) { |
| 239 | void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); |
| 240 | if (resume_backup_memory) { |
| 241 | *(u32 *)CBMEM_BOOT_MODE = 2; |
| 242 | *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; |
| 243 | } |
| 244 | /* Magic for S3 resume */ |
| 245 | pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); |
| 246 | } else { |
| 247 | pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); |
| 248 | } |
| 249 | #endif |
| 250 | } |