Angel Pons | 54c5472 | 2020-04-05 13:20:54 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 2 | |
| 3 | #include <stdint.h> |
Vladimir Serbinenko | 421b340 | 2016-02-10 02:39:51 +0100 | [diff] [blame] | 4 | #include <northbridge/intel/sandybridge/raminit.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 5 | #include <southbridge/intel/bd82x6x/pch.h> |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 6 | |
Arthur Heymans | 9c53834 | 2019-11-12 16:42:33 +0100 | [diff] [blame] | 7 | void mainboard_late_rcba_config(void) |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 8 | { |
Kyösti Mälkki | 6f49906 | 2015-06-06 11:52:24 +0300 | [diff] [blame] | 9 | /* |
| 10 | * GFX INTA -> PIRQA (MSI) |
| 11 | * D28IP_P1IP WLAN INTA -> PIRQB |
| 12 | * D28IP_P2IP ETH0 INTB -> PIRQF |
| 13 | * D28IP_P3IP SDCARD INTC -> PIRQD |
| 14 | * D29IP_E1P EHCI1 INTA -> PIRQD |
| 15 | * D26IP_E2P EHCI2 INTA -> PIRQF |
| 16 | * D31IP_SIP SATA INTA -> PIRQB (MSI) |
| 17 | * D31IP_SMIP SMBUS INTB -> PIRQH |
| 18 | * D31IP_TTIP THRT INTC -> PIRQA |
| 19 | * D27IP_ZIP HDA INTA -> PIRQA (MSI) |
| 20 | * |
| 21 | * Trackpad interrupt is edge triggered and cannot be shared. |
| 22 | * TRACKPAD -> PIRQG |
| 23 | |
| 24 | */ |
| 25 | |
| 26 | /* Device interrupt pin register (board specific) */ |
| 27 | RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | |
| 28 | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); |
| 29 | RCBA32(D29IP) = (INTA << D29IP_E1P); |
| 30 | RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | |
| 31 | (INTC << D28IP_P3IP); |
| 32 | RCBA32(D27IP) = (INTA << D27IP_ZIP); |
| 33 | RCBA32(D26IP) = (INTA << D26IP_E2P); |
| 34 | RCBA32(D25IP) = (NOINT << D25IP_LIP); |
| 35 | RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); |
| 36 | |
| 37 | /* Device interrupt route registers */ |
| 38 | DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); |
| 39 | DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); |
| 40 | DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); |
| 41 | DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); |
| 42 | DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); |
| 43 | DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 44 | DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 45 | } |
| 46 | |
Vladimir Serbinenko | 421b340 | 2016-02-10 02:39:51 +0100 | [diff] [blame] | 47 | void mainboard_fill_pei_data(struct pei_data *pei_data) |
| 48 | { |
Keith Hui | 7039edd | 2023-07-21 10:12:05 -0400 | [diff] [blame] | 49 | /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */ |
Vladimir Serbinenko | 421b340 | 2016-02-10 02:39:51 +0100 | [diff] [blame] | 50 | } |