Michał Żygowski | 72f06ca | 2020-04-13 21:42:24 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <stdint.h> |
| 4 | #include <arch/io.h> |
| 5 | #include <console/console.h> |
| 6 | #include <northbridge/intel/sandybridge/sandybridge.h> |
Michał Żygowski | 8ddbc7d | 2021-11-21 17:40:05 +0100 | [diff] [blame] | 7 | #include <southbridge/intel/common/rcba.h> |
Michał Żygowski | 72f06ca | 2020-04-13 21:42:24 +0200 | [diff] [blame] | 8 | #include <southbridge/intel/bd82x6x/pch.h> |
| 9 | #include <superio/smsc/sch5545/sch5545.h> |
| 10 | #include <superio/smsc/sch5545/sch5545_emi.h> |
| 11 | |
Michał Żygowski | 7e8b597 | 2022-02-20 23:27:18 +0100 | [diff] [blame] | 12 | #include <baseboard/sch5545_ec.h> |
Michał Żygowski | 72f06ca | 2020-04-13 21:42:24 +0200 | [diff] [blame] | 13 | |
Michał Żygowski | 8ddbc7d | 2021-11-21 17:40:05 +0100 | [diff] [blame] | 14 | void mainboard_late_rcba_config(void) |
| 15 | { |
| 16 | DIR_ROUTE(D31IR, PIRQA, PIRQD, PIRQC, PIRQA); |
| 17 | DIR_ROUTE(D29IR, PIRQH, PIRQD, PIRQA, PIRQC); |
| 18 | DIR_ROUTE(D28IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 19 | DIR_ROUTE(D27IR, PIRQG, PIRQB, PIRQC, PIRQD); |
| 20 | DIR_ROUTE(D26IR, PIRQA, PIRQF, PIRQC, PIRQD); |
| 21 | DIR_ROUTE(D25IR, PIRQE, PIRQF, PIRQG, PIRQH); |
| 22 | DIR_ROUTE(D22IR, PIRQA, PIRQD, PIRQC, PIRQB); |
| 23 | DIR_ROUTE(D20IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 24 | } |
| 25 | |
Michał Żygowski | 72f06ca | 2020-04-13 21:42:24 +0200 | [diff] [blame] | 26 | void mainboard_early_init(int s3resume) |
| 27 | { |
| 28 | uint16_t ec_fw_version; |
| 29 | |
| 30 | /* |
| 31 | * We do EC initialization in romstage, because it makes no sense to |
| 32 | * bloat the bootblock any more. Secondly, the EC expects to receive |
| 33 | * correct initialization sequence from the host in the time window of |
| 34 | * about 3-5 seconds since system reset. If it doesn't receive the |
| 35 | * initialization sequence, it enters an error path which results in |
| 36 | * fans spinned up to high speed. In this state EC doesn't respond to |
| 37 | * further messages sent over EMI. The issue appears after power |
| 38 | * failure, where EC loses its configuration. For this particular |
| 39 | * reasons we do the initialization in romstage instead of ramstage. |
| 40 | */ |
| 41 | sch5545_emi_init(0x2e); |
| 42 | if (sch5545_emi_get_int_mask_high()) |
| 43 | printk(BIOS_SPEW, "EC interrupt mask MSB is not 0\n"); |
| 44 | |
| 45 | sch5545_ec_hwm_early_init(); |
| 46 | |
| 47 | if (!s3resume) { |
| 48 | ec_fw_version = sch5545_get_ec_fw_version(); |
| 49 | printk(BIOS_DEBUG, "SCH5545 EC firmware version %04x\n", ec_fw_version); |
| 50 | sch5545_update_ec_firmware(ec_fw_version); |
| 51 | } |
| 52 | printk(BIOS_DEBUG, "EC early init complete.\n"); |
| 53 | |
| 54 | /* Disable SMIs and clear SMI status */ |
| 55 | outb(0, SCH5545_RUNTIME_REG_BASE + SCH5545_RR_SMI_EN); |
| 56 | outb(SCH5545_SMI_GLOBAL_STS, SCH5545_RUNTIME_REG_BASE + SCH5545_RR_SMI_STS); |
| 57 | } |