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review.coreboot.org / coreboot / a911b758482025d46e132eeb2ed0279b65692075 / . / src / mainboard / asus / p8x7x-series / variants / p8z77-m_pro / cmos.layout
blob: 3d717b444d954bcee50460a997926e76931ce77e [file] [log] [blame]
Patrick Georgic49d7a32020-05-08 22:50:46 +0200[diff] [blame]1## SPDX-License-Identifier: GPL-2.0-only
Vlado Cibic2bf6a302019-06-09 06:53:50 +0000[diff] [blame]2
3# -----------------------------------------------------------------
4entries
5
6# -----------------------------------------------------------------
Angel Ponsc85cce02020-11-03 00:29:39 +0100[diff] [blame]70 120 r 0 reserved_memory
Vlado Cibic2bf6a302019-06-09 06:53:50 +0000[diff] [blame]8
9# -----------------------------------------------------------------
10# RTC_BOOT_BYTE (coreboot hardcoded)
Angel Ponsc85cce02020-11-03 00:29:39 +0100[diff] [blame]11384 1 e 3 boot_option
12388 4 h 0 reboot_counter
Vlado Cibic2bf6a302019-06-09 06:53:50 +0000[diff] [blame]13
14# -----------------------------------------------------------------
15# coreboot config options: console
Angel Ponsc85cce02020-11-03 00:29:39 +0100[diff] [blame]16395 4 e 4 debug_level
17#400 8 r 0 reserved for century byte
Vlado Cibic2bf6a302019-06-09 06:53:50 +0000[diff] [blame]18
19# -----------------------------------------------------------------
20# coreboot config options: southbridge
21
22# Non Maskable Interrupt(NMI) support, which is an interrupt that may
23# occur on a RAM or unrecoverable error.
Angel Ponsc85cce02020-11-03 00:29:39 +0100[diff] [blame]24408 1 e 1 nmi
Vlado Cibic2bf6a302019-06-09 06:53:50 +0000[diff] [blame]25
Angel Ponsc85cce02020-11-03 00:29:39 +0100[diff] [blame]26409 2 e 5 power_on_after_fail
27411 1 e 6 sata_mode
Vlado Cibic2bf6a302019-06-09 06:53:50 +0000[diff] [blame]28
29# -----------------------------------------------------------------
30# coreboot config options: northbridge
31
32# gfx_uma_size
33# Quantity of shared video memory the IGP can use
34#
Angel Ponsc85cce02020-11-03 00:29:39 +0100[diff] [blame]35416 5 e 7 gfx_uma_size
Vlado Cibic2bf6a302019-06-09 06:53:50 +0000[diff] [blame]36
37# -----------------------------------------------------------------
38# coreboot config options: usb3
39
40# usb3_mode
41# Controls how the motherboard's USB3 ports act at boot time
Angel Ponsc85cce02020-11-03 00:29:39 +0100[diff] [blame]42421 2 e 8 usb3_mode
Vlado Cibic2bf6a302019-06-09 06:53:50 +0000[diff] [blame]43
44# usb3_drv
Elyes HAOUAS6dc9d032020-02-16 16:22:52 +0100[diff] [blame]45# Load (or not) pre-OS xHCI USB3 BIOS driver
Vlado Cibic2bf6a302019-06-09 06:53:50 +0000[diff] [blame]46#
Angel Ponsc85cce02020-11-03 00:29:39 +0100[diff] [blame]47423 1 e 1 usb3_drv
Vlado Cibic2bf6a302019-06-09 06:53:50 +0000[diff] [blame]48
49# usb3_streams
50# Streams can provide more speed (as they can use 64Kb packets),
51# but they might cause incompatibilities with some devices.
52#
Angel Ponsc85cce02020-11-03 00:29:39 +0100[diff] [blame]53424 1 e 1 usb3_streams
Vlado Cibic2bf6a302019-06-09 06:53:50 +0000[diff] [blame]54
55# -----------------------------------------------------------------
56# Sandy/Ivy Bridge MRC Scrambler Seed values
57# note: MUST NOT be covered by checksum!
Angel Ponsc85cce02020-11-03 00:29:39 +0100[diff] [blame]58464 32 r 0 mrc_scrambler_seed
59496 32 r 0 mrc_scrambler_seed_s3
60528 16 r 0 mrc_scrambler_seed_chk
Vlado Cibic2bf6a302019-06-09 06:53:50 +0000[diff] [blame]61
62# -----------------------------------------------------------------
63# coreboot config options: check sums
Angel Ponsc85cce02020-11-03 00:29:39 +0100[diff] [blame]64544 16 h 0 check_sum
Vlado Cibic2bf6a302019-06-09 06:53:50 +0000[diff] [blame]65
66# -----------------------------------------------------------------
67
68enumerations
Angel Ponsc85cce02020-11-03 00:29:39 +0100[diff] [blame]69#ID value text
Vlado Cibic2bf6a302019-06-09 06:53:50 +0000[diff] [blame]70
71# Generic on/off enum
Angel Ponsc85cce02020-11-03 00:29:39 +0100[diff] [blame]721 0 Disable
731 1 Enable
Vlado Cibic2bf6a302019-06-09 06:53:50 +0000[diff] [blame]74
75# boot_option
Angel Ponsc85cce02020-11-03 00:29:39 +0100[diff] [blame]763 0 Fallback
773 1 Normal
Vlado Cibic2bf6a302019-06-09 06:53:50 +0000[diff] [blame]78
79# debug_level
Angel Ponsc85cce02020-11-03 00:29:39 +0100[diff] [blame]804 0 Emergency
814 1 Alert
824 2 Critical
834 3 Error
844 4 Warning
854 5 Notice
864 6 Info
874 7 Debug
884 8 Spew
Vlado Cibic2bf6a302019-06-09 06:53:50 +0000[diff] [blame]89
90# power_on_after_fail
Angel Ponsc85cce02020-11-03 00:29:39 +0100[diff] [blame]915 0 Disable
925 1 Enable
935 2 Keep
Vlado Cibic2bf6a302019-06-09 06:53:50 +0000[diff] [blame]94
95# sata_mode
Angel Ponsc85cce02020-11-03 00:29:39 +0100[diff] [blame]966 0 AHCI
976 1 Compatible
Vlado Cibic2bf6a302019-06-09 06:53:50 +0000[diff] [blame]98
99# gfx_uma_size (Intel IGP Video RAM size)
Angel Ponsc85cce02020-11-03 00:29:39 +0100[diff] [blame]1007 0 32M
1017 1 64M
1027 2 96M
1037 3 128M
1047 4 160M
1057 5 192M
1067 6 224M
1077 7 256M
1087 8 288M
1097 9 320M
1107 10 352M
1117 11 384M
1127 12 416M
1137 13 448M
1147 14 480M
1157 15 512M
1167 16 544M
1177 17 576M
1187 18 608M
1197 19 640M
1207 20 672M
1217 21 704M
1227 22 736M
1237 23 768M
1247 24 800M
1257 25 832M
1267 26 864M
1277 27 896M
1287 28 928M
1297 29 960M
1307 30 992M
Vlado Cibic2bf6a302019-06-09 06:53:50 +0000[diff] [blame]131
132# usb3_mode
133# Disable = Use the port always as USB 2.0 for compatibility
134# Enable = Use the port always as USB 3.0 for speed
135# Auto = Initialize the port as USB 2.0, until the OS loads
Angel Ponsc85cce02020-11-03 00:29:39 +0100[diff] [blame]136# xHCI USB 3.0 driver
Vlado Cibic2bf6a302019-06-09 06:53:50 +0000[diff] [blame]137# SmartAuto = Same as Auto but, if the OS loads the xHCI USB 3.0 driver
Angel Ponsc85cce02020-11-03 00:29:39 +0100[diff] [blame]138# and the computer is reset, keep the USB 3.0 mode.
Vlado Cibic2bf6a302019-06-09 06:53:50 +0000[diff] [blame]139#
Angel Ponsc85cce02020-11-03 00:29:39 +0100[diff] [blame]1408 0 Disable
1418 1 Enable
1428 2 Auto
1438 3 SmartAuto
Vlado Cibic2bf6a302019-06-09 06:53:50 +0000[diff] [blame]144
145# -----------------------------------------------------------------
146# <startBit[must be byte-aligned]> <endBit[must be byte aligned]>
Angel Ponsc85cce02020-11-03 00:29:39 +0100[diff] [blame]147# <bit where to start storing checksum[must be 16bits-aligned]>
Vlado Cibic2bf6a302019-06-09 06:53:50 +0000[diff] [blame]148checksums
149
150checksum 392 431 544