| Alice Sell | cebf1e8 | 2021-06-17 17:09:00 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <bootblock_common.h> |
| 4 | #include <device/pnp_ops.h> |
| Alice Sell | cebf1e8 | 2021-06-17 17:09:00 -0700 | [diff] [blame] | 5 | #include <southbridge/intel/bd82x6x/pch.h> |
| 6 | #include <superio/nuvoton/common/nuvoton.h> |
| 7 | #include <superio/nuvoton/nct6776/nct6776.h> |
| 8 | |
| 9 | #define GLOBAL_DEV PNP_DEV(0x2e, 0) |
| 10 | #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) |
| 11 | #define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) |
| 12 | |
| Alice Sell | cebf1e8 | 2021-06-17 17:09:00 -0700 | [diff] [blame] | 13 | void bootblock_mainboard_early_init(void) |
| 14 | { |
| 15 | nuvoton_pnp_enter_conf_state(GLOBAL_DEV); |
| 16 | |
| 17 | /* Select SIO pin states. */ |
| 18 | pnp_write_config(GLOBAL_DEV, 0x1c, 0x83); |
| 19 | pnp_write_config(GLOBAL_DEV, 0x24, 0x30); |
| 20 | pnp_write_config(GLOBAL_DEV, 0x27, 0x40); |
| 21 | pnp_write_config(GLOBAL_DEV, 0x2a, 0x20); |
| 22 | |
| 23 | /* Power RAM in S3. */ |
| 24 | pnp_set_logical_device(ACPI_DEV); |
| 25 | pnp_write_config(ACPI_DEV, 0xe4, 0x10); |
| 26 | |
| 27 | pnp_set_logical_device(SERIAL_DEV); |
| 28 | |
| 29 | nuvoton_pnp_exit_conf_state(GLOBAL_DEV); |
| 30 | |
| 31 | /* Enable UART */ |
| 32 | nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
| 33 | } |