blob: 6f2647927e4b04aac3162505cc9c01a6ee123089 [file] [log] [blame]
Uwe Hermann2bb4acf2010-03-01 17:19:55 +00001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2007-2008 coresystems GmbH
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
15## You should have received a copy of the GNU General Public License
16## along with this program; if not, write to the Free Software
17## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18##
Stefan Reinauer36a22682008-10-29 04:52:57 +000019
20# -----------------------------------------------------------------
21entries
22
23#start-bit length config config-ID name
24#0 8 r 0 seconds
25#8 8 r 0 alarm_seconds
26#16 8 r 0 minutes
27#24 8 r 0 alarm_minutes
28#32 8 r 0 hours
29#40 8 r 0 alarm_hours
30#48 8 r 0 day_of_week
31#56 8 r 0 day_of_month
32#64 8 r 0 month
33#72 8 r 0 year
34# -----------------------------------------------------------------
35# Status Register A
36#80 4 r 0 rate_select
37#84 3 r 0 REF_Clock
38#87 1 r 0 UIP
39# -----------------------------------------------------------------
40# Status Register B
41#88 1 r 0 auto_switch_DST
42#89 1 r 0 24_hour_mode
43#90 1 r 0 binary_values_enable
44#91 1 r 0 square-wave_out_enable
45#92 1 r 0 update_finished_enable
46#93 1 r 0 alarm_interrupt_enable
47#94 1 r 0 periodic_interrupt_enable
48#95 1 r 0 disable_clock_updates
49# -----------------------------------------------------------------
50# Status Register C
51#96 4 r 0 status_c_rsvd
52#100 1 r 0 uf_flag
53#101 1 r 0 af_flag
54#102 1 r 0 pf_flag
55#103 1 r 0 irqf_flag
56# -----------------------------------------------------------------
57# Status Register D
58#104 7 r 0 status_d_rsvd
59#111 1 r 0 valid_cmos_ram
60# -----------------------------------------------------------------
61# Diagnostic Status Register
62#112 8 r 0 diag_rsvd1
63
64# -----------------------------------------------------------------
650 120 r 0 reserved_memory
66#120 264 r 0 unused
67
68# -----------------------------------------------------------------
69# RTC_BOOT_BYTE (coreboot hardcoded)
70384 1 e 4 boot_option
71385 1 e 4 last_boot
72388 4 r 0 reboot_bits
73#390 2 r 0 unused?
74
75# -----------------------------------------------------------------
76# coreboot config options: console
77392 3 e 5 baud_rate
78395 4 e 6 debug_level
79#399 1 r 0 unused
80
81# coreboot config options: cpu
82400 1 e 2 hyper_threading
83#401 7 r 0 unused
84
85# coreboot config options: southbridge
86408 1 e 1 nmi
Stefan Reinauera5fdadf2009-07-21 21:58:20 +000087409 2 e 7 power_on_after_fail
88#411 5 r 0 unused
Stefan Reinauer36a22682008-10-29 04:52:57 +000089
Luc Verhaegen9efecc52009-06-03 14:19:20 +000090# coreboot config options: bootloader
91416 512 s 0 boot_devices
Stefan Reinauerbf264e92010-05-14 19:09:20 +000092928 8 h 0 boot_default
Patrick Georgia865b172011-01-14 07:40:24 +000093936 1 e 11 cmos_defaults_loaded
94#937 11 r 0 unused
Stefan Reinaueraca6ec62009-10-26 17:12:21 +000095
96# coreboot config options: mainboard specific options
97948 2 e 8 cpufan_cruise_control
98950 2 e 8 sysfan_cruise_control
99952 4 e 9 cpufan_speed
100#956 4 e 10 cpufan_temperature
101960 4 e 9 sysfan_speed
102#964 4 e 10 sysfan_temperature
103
104968 1 e 2 ethernet1
105969 1 e 2 ethernet2
106970 1 e 2 ethernet3
Stefan Reinauer14e22772010-04-27 06:56:47 +0000107
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000108#971 13 r 0 unused
Stefan Reinauer36a22682008-10-29 04:52:57 +0000109
110# coreboot config options: check sums
111984 16 h 0 check_sum
112#1000 24 r 0 amd_reserved
113
Stefan Reinauera5fdadf2009-07-21 21:58:20 +0000114# ram initialization internal data
1151024 8 r 0 C0WL0REOST
1161032 8 r 0 C1WL0REOST
1171040 8 r 0 RCVENMT
1181048 4 r 0 C0DRT1
1191052 4 r 0 C1DRT1
120
Stefan Reinauer36a22682008-10-29 04:52:57 +0000121# -----------------------------------------------------------------
122
123enumerations
124
125#ID value text
1261 0 Disable
1271 1 Enable
1282 0 Enable
1292 1 Disable
1304 0 Fallback
1314 1 Normal
1325 0 115200
1335 1 57600
1345 2 38400
1355 3 19200
1365 4 9600
1375 5 4800
1385 6 2400
1395 7 1200
1406 1 Emergency
1416 2 Alert
1426 3 Critical
1436 4 Error
1446 5 Warning
1456 6 Notice
1466 7 Info
1476 8 Debug
1486 9 Spew
Stefan Reinauera5fdadf2009-07-21 21:58:20 +00001497 0 Disable
1507 1 Enable
1517 2 Keep
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000152# Fan Cruise Control
1538 0 Disabled
1548 1 Speed
155#8 2 Thermal
156# Fan Speed (Rotations per Minute)
1579 0 5625
1589 1 5192
1599 2 4753
1609 3 4326
1619 4 3924
1629 5 3552
1639 6 3214
1649 7 2909
1659 8 2636
1669 9 2393
1679 10 2177
1689 11 1985
1699 12 1814
1709 13 1662
1719 14 1527
1729 15 1406
173#
174# Temperature (°C/°F)
175#10 0 30/86
176#10 1 33/91
177#10 2 36/96
178#10 3 39/102
179#10 4 42/107
180#10 5 45/113
181#10 6 48/118
182#10 7 51/123
183#10 8 54/129
184#10 9 57/134
185#10 10 60/140
186#10 11 63/145
187#10 12 66/150
188#10 13 69/156
189#10 14 72/161
190#10 15 75/167
Patrick Georgia865b172011-01-14 07:40:24 +000019111 0 No
19211 1 Yes
Stefan Reinauer36a22682008-10-29 04:52:57 +0000193# -----------------------------------------------------------------
194checksums
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196checksum 392 983 984
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