Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com> |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame^] | 5 | * Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 6 | * Copyright (C) 2007-2008 coresystems GmbH |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame^] | 7 | * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com> |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; version 2 of the License. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 21 | */ |
| 22 | |
| 23 | #include <cpu/x86/stack.h> |
| 24 | #include <cpu/x86/mtrr.h> |
| 25 | #include <cpu/x86/post_code.h> |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 26 | #include <cpu/x86/lapic_def.h> |
| 27 | |
| 28 | /* Macro to access Local APIC registers at default base. */ |
| 29 | #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame^] | 30 | #define START_IPI_VECTOR ((CONFIG_AP_SIPI_VECTOR >> 12) & 0xff) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 31 | |
| 32 | #define CPU_MAXPHYADDR 36 |
| 33 | #define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) |
| 34 | |
Kyösti Mälkki | 325b92f | 2012-02-28 00:24:15 +0200 | [diff] [blame] | 35 | /* Base address to cache all of Flash ROM, just below 4GB. */ |
| 36 | #define CACHE_ROM_BASE ((1<<22 - CONFIG_CACHE_ROM_SIZE>>10)<<10) |
| 37 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 38 | #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE |
| 39 | #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE |
| 40 | |
| 41 | /* Save the BIST result. */ |
| 42 | movl %eax, %ebp |
| 43 | |
| 44 | cache_as_ram: |
| 45 | post_code(0x20) |
| 46 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame^] | 47 | /* Zero out all fixed range and variable range MTRRs. |
| 48 | * For hyper-threaded CPU MTRRs are shared so we actually |
| 49 | * clear them more than once, but we don't care. */ |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 50 | movl $mtrr_table, %esi |
| 51 | movl $((mtrr_table_end - mtrr_table) / 2), %edi |
| 52 | xorl %eax, %eax |
| 53 | xorl %edx, %edx |
| 54 | clear_mtrrs: |
| 55 | movw (%esi), %bx |
| 56 | movzx %bx, %ecx |
| 57 | wrmsr |
| 58 | add $2, %esi |
| 59 | dec %edi |
| 60 | jnz clear_mtrrs |
| 61 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame^] | 62 | post_code(0x21) |
| 63 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 64 | /* Configure the default memory type to uncacheable. */ |
| 65 | movl $MTRRdefType_MSR, %ecx |
| 66 | rdmsr |
| 67 | andl $(~0x00000cff), %eax |
| 68 | wrmsr |
| 69 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame^] | 70 | post_code(0x22) |
| 71 | |
| 72 | /* Enable local apic. */ |
| 73 | movl $LAPIC_BASE_MSR, %ecx |
| 74 | rdmsr |
| 75 | andl $(~CPU_PHYSMASK_HI), %edx |
| 76 | andl $(~LAPIC_BASE_MSR_ADDR_MASK), %eax |
| 77 | orl $(LAPIC_DEFAULT_BASE | LAPIC_BASE_MSR_ENABLE), %eax |
| 78 | wrmsr |
| 79 | andl $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax |
| 80 | jz ap_init |
| 81 | |
| 82 | bsp_init: |
| 83 | |
| 84 | post_code(0x23) |
| 85 | |
| 86 | /* Send INIT IPI to all excluding ourself. */ |
| 87 | movl LAPIC(ICR), %edi |
| 88 | movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax |
| 89 | 1: movl %eax, (%edi) |
| 90 | movl $0x30, %ecx |
| 91 | 2: pause |
| 92 | dec %ecx |
| 93 | jnz 2b |
| 94 | movl (%edi), %ecx |
| 95 | andl $LAPIC_ICR_BUSY, %ecx |
| 96 | jnz 1b |
| 97 | |
| 98 | post_code(0x24) |
| 99 | |
| 100 | /* For a hyper-threading processor, cache must not be disabled |
| 101 | * on an AP on the same physical package with the BSP. |
| 102 | */ |
| 103 | movl $01, %eax |
| 104 | cpuid |
| 105 | btl $28, %edx |
| 106 | jnc sipi_complete |
| 107 | bswapl %ebx |
| 108 | cmpb $01, %bh |
| 109 | jbe sipi_complete |
| 110 | |
| 111 | hyper_threading_cpu: |
| 112 | |
| 113 | /* delay 10 ms */ |
| 114 | movl $10000, %ecx |
| 115 | 1: inb $0x80, %al |
| 116 | dec %ecx |
| 117 | jnz 1b |
| 118 | |
| 119 | post_code(0x25) |
| 120 | |
| 121 | /* Send Start IPI to all excluding ourself. */ |
| 122 | movl LAPIC(ICR), %edi |
| 123 | movl $(LAPIC_DEST_ALLBUT | LAPIC_DM_STARTUP | START_IPI_VECTOR), %eax |
| 124 | 1: movl %eax, (%edi) |
| 125 | movl $0x30, %ecx |
| 126 | 2: pause |
| 127 | dec %ecx |
| 128 | jnz 2b |
| 129 | movl (%edi), %ecx |
| 130 | andl $LAPIC_ICR_BUSY, %ecx |
| 131 | jnz 1b |
| 132 | |
| 133 | /* delay 250 us */ |
| 134 | movl $250, %ecx |
| 135 | 1: inb $0x80, %al |
| 136 | dec %ecx |
| 137 | jnz 1b |
| 138 | |
| 139 | post_code(0x26) |
| 140 | |
| 141 | /* Wait for sibling CPU to start. */ |
| 142 | 1: movl $(MTRRphysBase_MSR(0)), %ecx |
| 143 | rdmsr |
| 144 | andl %eax, %eax |
| 145 | jnz sipi_complete |
| 146 | |
| 147 | movl $0x30, %ecx |
| 148 | 2: pause |
| 149 | dec %ecx |
| 150 | jnz 2b |
| 151 | jmp 1b |
| 152 | |
| 153 | |
| 154 | ap_init: |
| 155 | post_code(0x27) |
| 156 | |
| 157 | /* Do not disable cache (so BSP can enable it). */ |
| 158 | movl %cr0, %eax |
| 159 | andl $(~((1 << 30) | (1 << 29))), %eax |
| 160 | movl %eax, %cr0 |
| 161 | |
| 162 | post_code(0x28) |
| 163 | |
| 164 | /* MTRR registers are shared between HT siblings. */ |
| 165 | movl $(MTRRphysBase_MSR(0)), %ecx |
| 166 | movl $(1<<12), %eax |
| 167 | xorl %edx, %edx |
| 168 | wrmsr |
| 169 | |
| 170 | post_code(0x29) |
| 171 | |
| 172 | ap_halt: |
| 173 | cli |
| 174 | 1: hlt |
| 175 | jnz 1b |
| 176 | |
| 177 | |
| 178 | |
| 179 | sipi_complete: |
| 180 | |
| 181 | post_code(0x2a) |
| 182 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 183 | /* Set Cache-as-RAM base address. */ |
| 184 | movl $(MTRRphysBase_MSR(0)), %ecx |
| 185 | movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax |
| 186 | xorl %edx, %edx |
| 187 | wrmsr |
| 188 | |
| 189 | /* Set Cache-as-RAM mask. */ |
| 190 | movl $(MTRRphysMask_MSR(0)), %ecx |
| 191 | movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax |
| 192 | movl $CPU_PHYSMASK_HI, %edx |
| 193 | wrmsr |
| 194 | |
| 195 | /* Enable MTRR. */ |
| 196 | movl $MTRRdefType_MSR, %ecx |
| 197 | rdmsr |
| 198 | orl $MTRRdefTypeEn, %eax |
| 199 | wrmsr |
| 200 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame^] | 201 | post_code(0x2b) |
| 202 | |
Kyösti Mälkki | 05d6ffb | 2012-02-16 23:12:04 +0200 | [diff] [blame] | 203 | /* Enable L2 cache Write-Back (WBINVD and FLUSH#). |
| 204 | * |
| 205 | * MSR is set when DisplayFamily_DisplayModel is one of: |
| 206 | * 06_0x, 06_17, 06_1C |
| 207 | * |
| 208 | * Description says this bit enables use of WBINVD and FLUSH#. |
| 209 | * Should this be set only after the system bus and/or memory |
| 210 | * controller can successfully handle write cycles? |
| 211 | */ |
| 212 | |
| 213 | #define EAX_FAMILY(a) (a << 8) /* for family <= 0fH */ |
| 214 | #define EAX_MODEL(a) (((a & 0xf0) << 12) | ((a & 0xf) << 4)) |
| 215 | |
| 216 | movl $1, %eax |
| 217 | cpuid |
| 218 | movl %eax, %ebx |
| 219 | andl $EAX_FAMILY(0x0f), %eax |
| 220 | cmpl $EAX_FAMILY(0x06), %eax |
| 221 | jne no_msr_11e |
| 222 | movl %ebx, %eax |
| 223 | andl $EAX_MODEL(0xff), %eax |
| 224 | cmpl $EAX_MODEL(0x17), %eax |
| 225 | je has_msr_11e |
| 226 | cmpl $EAX_MODEL(0x1c), %eax |
| 227 | je has_msr_11e |
| 228 | andl $EAX_MODEL(0xf0), %eax |
| 229 | cmpl $EAX_MODEL(0x00), %eax |
| 230 | jne no_msr_11e |
| 231 | has_msr_11e: |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 232 | movl $0x11e, %ecx |
| 233 | rdmsr |
| 234 | orl $(1 << 8), %eax |
| 235 | wrmsr |
Kyösti Mälkki | 05d6ffb | 2012-02-16 23:12:04 +0200 | [diff] [blame] | 236 | no_msr_11e: |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 237 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame^] | 238 | post_code(0x2c) |
| 239 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 240 | /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 241 | movl %cr0, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 242 | andl $(~((1 << 30) | (1 << 29))), %eax |
| 243 | invd |
| 244 | movl %eax, %cr0 |
| 245 | |
| 246 | /* Clear the cache memory reagion. */ |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 247 | cld |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 248 | xorl %eax, %eax |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 249 | movl $CACHE_AS_RAM_BASE, %edi |
| 250 | movl $(CACHE_AS_RAM_SIZE / 4), %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 251 | rep stosl |
| 252 | |
| 253 | /* Enable Cache-as-RAM mode by disabling cache. */ |
| 254 | movl %cr0, %eax |
| 255 | orl $(1 << 30), %eax |
| 256 | movl %eax, %cr0 |
| 257 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame^] | 258 | post_code(0x2d) |
| 259 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 260 | #if CONFIG_XIP_ROM_SIZE |
| 261 | /* Enable cache for our code in Flash because we do XIP here */ |
| 262 | movl $MTRRphysBase_MSR(1), %ecx |
| 263 | xorl %edx, %edx |
| 264 | /* |
| 265 | * IMPORTANT: The following calculation _must_ be done at runtime. See |
| 266 | * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html |
| 267 | */ |
| 268 | movl $copy_and_run, %eax |
| 269 | andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax |
| 270 | orl $MTRR_TYPE_WRBACK, %eax |
| 271 | wrmsr |
| 272 | |
| 273 | movl $MTRRphysMask_MSR(1), %ecx |
| 274 | movl $CPU_PHYSMASK_HI, %edx |
| 275 | movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax |
| 276 | wrmsr |
| 277 | #endif /* CONFIG_XIP_ROM_SIZE */ |
| 278 | |
| 279 | /* Enable cache. */ |
| 280 | movl %cr0, %eax |
| 281 | andl $(~((1 << 30) | (1 << 29))), %eax |
| 282 | movl %eax, %cr0 |
| 283 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame^] | 284 | post_code(0x2e) |
| 285 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 286 | /* Set up the stack pointer. */ |
| 287 | #if CONFIG_USBDEBUG |
| 288 | /* Leave some space for the struct ehci_debug_info. */ |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 289 | movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %esp |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 290 | #else |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 291 | movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %esp |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 292 | #endif |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 293 | |
| 294 | /* Restore the BIST result. */ |
| 295 | movl %ebp, %eax |
| 296 | movl %esp, %ebp |
| 297 | pushl %eax |
| 298 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame^] | 299 | post_code(0x2f) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 300 | |
| 301 | /* Call romstage.c main function. */ |
| 302 | call main |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 303 | addl $4, %esp |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 304 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 305 | post_code(0x30) |
| 306 | |
| 307 | /* Disable cache. */ |
| 308 | movl %cr0, %eax |
| 309 | orl $(1 << 30), %eax |
| 310 | movl %eax, %cr0 |
| 311 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame^] | 312 | post_code(0x34) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 313 | |
| 314 | /* Disable MTRR. */ |
| 315 | movl $MTRRdefType_MSR, %ecx |
| 316 | rdmsr |
| 317 | andl $(~MTRRdefTypeEn), %eax |
| 318 | wrmsr |
| 319 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame^] | 320 | post_code(0x35) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 321 | |
| 322 | invd |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 323 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame^] | 324 | post_code(0x36) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 325 | |
| 326 | /* Enable cache. */ |
| 327 | movl %cr0, %eax |
| 328 | andl $~((1 << 30) | (1 << 29)), %eax |
| 329 | movl %eax, %cr0 |
| 330 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame^] | 331 | post_code(0x37) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 332 | |
| 333 | /* Disable cache. */ |
| 334 | movl %cr0, %eax |
| 335 | orl $(1 << 30), %eax |
| 336 | movl %eax, %cr0 |
| 337 | |
| 338 | post_code(0x38) |
| 339 | |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 340 | /* Enable Write Back and Speculative Reads for low RAM. */ |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 341 | movl $MTRRphysBase_MSR(0), %ecx |
| 342 | movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax |
| 343 | xorl %edx, %edx |
| 344 | wrmsr |
| 345 | movl $MTRRphysMask_MSR(0), %ecx |
| 346 | movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax |
| 347 | movl $CPU_PHYSMASK_HI, %edx |
| 348 | wrmsr |
| 349 | |
Kyösti Mälkki | 325b92f | 2012-02-28 00:24:15 +0200 | [diff] [blame] | 350 | /* Enable caching and Speculative Reads for Flash ROM device. */ |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 351 | movl $MTRRphysBase_MSR(1), %ecx |
Kyösti Mälkki | 325b92f | 2012-02-28 00:24:15 +0200 | [diff] [blame] | 352 | movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 353 | xorl %edx, %edx |
| 354 | wrmsr |
| 355 | movl $MTRRphysMask_MSR(1), %ecx |
Kyösti Mälkki | 325b92f | 2012-02-28 00:24:15 +0200 | [diff] [blame] | 356 | movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 357 | movl $CPU_PHYSMASK_HI, %edx |
| 358 | wrmsr |
| 359 | |
| 360 | post_code(0x39) |
| 361 | |
| 362 | /* And enable cache again after setting MTRRs. */ |
| 363 | movl %cr0, %eax |
| 364 | andl $~((1 << 30) | (1 << 29)), %eax |
| 365 | movl %eax, %cr0 |
| 366 | |
| 367 | post_code(0x3a) |
| 368 | |
| 369 | /* Enable MTRR. */ |
| 370 | movl $MTRRdefType_MSR, %ecx |
| 371 | rdmsr |
| 372 | orl $MTRRdefTypeEn, %eax |
| 373 | wrmsr |
| 374 | |
| 375 | post_code(0x3b) |
| 376 | |
| 377 | /* Invalidate the cache again. */ |
| 378 | invd |
| 379 | |
| 380 | post_code(0x3c) |
| 381 | |
| 382 | /* Clear boot_complete flag. */ |
| 383 | xorl %ebp, %ebp |
| 384 | __main: |
| 385 | post_code(POST_PREPARE_RAMSTAGE) |
| 386 | cld /* Clear direction flag. */ |
| 387 | |
| 388 | movl %ebp, %esi |
| 389 | |
| 390 | movl $ROMSTAGE_STACK, %esp |
| 391 | movl %esp, %ebp |
| 392 | pushl %esi |
| 393 | call copy_and_run |
| 394 | |
| 395 | .Lhlt: |
| 396 | post_code(POST_DEAD_CODE) |
| 397 | hlt |
| 398 | jmp .Lhlt |
| 399 | |
| 400 | mtrr_table: |
| 401 | /* Fixed MTRRs */ |
| 402 | .word 0x250, 0x258, 0x259 |
| 403 | .word 0x268, 0x269, 0x26A |
| 404 | .word 0x26B, 0x26C, 0x26D |
| 405 | .word 0x26E, 0x26F |
| 406 | /* Variable MTRRs */ |
| 407 | .word 0x200, 0x201, 0x202, 0x203 |
| 408 | .word 0x204, 0x205, 0x206, 0x207 |
| 409 | .word 0x208, 0x209, 0x20A, 0x20B |
| 410 | .word 0x20C, 0x20D, 0x20E, 0x20F |
| 411 | mtrr_table_end: |
| 412 | |