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review.coreboot.org / coreboot / a7c96155b97db8bb7aac9b729c45bfdc1f8dda6d / . / src / superio / ite / common / ite.h
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Felix Held3f3eca92020-01-23 17:12:32 +0100[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-or-later */
Edward O'Callaghanf2920022014-04-27 00:41:50 +1000[diff] [blame]2
Arthur Heymans085a2262019-01-04 16:11:50 +0100[diff] [blame]3#ifndef SUPERIO_ITE_COMMON_PRE_RAM_H
4#define SUPERIO_ITE_COMMON_PRE_RAM_H
Edward O'Callaghanf2920022014-04-27 00:41:50 +1000[diff] [blame]5
Kyösti Mälkki3855c012019-03-03 08:45:19 +0200[diff] [blame]6#include <device/pnp_type.h>
Joel Linna7c96152024-03-26 18:35:15 +0100[diff] [blame^]7#include <stdbool.h>
Edward O'Callaghanf2920022014-04-27 00:41:50 +1000[diff] [blame]8#include <stdint.h>
9
10#define ITE_UART_CLK_PREDIVIDE_48 0x00 /* default */
11#define ITE_UART_CLK_PREDIVIDE_24 0x01
12
Edward O'Callaghan85836c22014-07-09 20:26:25 +1000[diff] [blame]13void ite_conf_clkin(pnp_devfn_t dev, u8 predivide);
14void ite_enable_serial(pnp_devfn_t dev, u16 iobase);
Edward O'Callaghanf2920022014-04-27 00:41:50 +1000[diff] [blame]15
16/* Some boards need to init wdt+gpio's very early */
Edward O'Callaghan85836c22014-07-09 20:26:25 +1000[diff] [blame]17void ite_reg_write(pnp_devfn_t dev, u8 reg, u8 value);
Joel Linna7c96152024-03-26 18:35:15 +0100[diff] [blame^]18void ite_set_3vsbsw(pnp_devfn_t dev, bool enable);
Michael Büchler6c5f47b2020-08-20 16:06:26 +0200[diff] [blame]19void ite_delay_pwrgd3(pnp_devfn_t dev);
Edward O'Callaghan85836c22014-07-09 20:26:25 +1000[diff] [blame]20void ite_kill_watchdog(pnp_devfn_t dev);
Joel Linnfb516612024-03-29 14:08:35 +0100[diff] [blame]21void ite_ac_resume_southbridge(pnp_devfn_t dev);
Edward O'Callaghanf2920022014-04-27 00:41:50 +1000[diff] [blame]22
Joel Linna7c96152024-03-26 18:35:15 +0100[diff] [blame^]23/* Alias for backwards compatibility */
24static inline void ite_enable_3vsbsw(pnp_devfn_t dev) { ite_set_3vsbsw(dev, true); }
25static inline void ite_disable_3vsbsw(pnp_devfn_t dev) { ite_set_3vsbsw(dev, false); }
26
Nico Huber61673652016-10-11 11:56:32 +0200[diff] [blame]27void pnp_enter_conf_state(pnp_devfn_t dev);
28void pnp_exit_conf_state(pnp_devfn_t dev);
29
Arthur Heymans085a2262019-01-04 16:11:50 +0100[diff] [blame]30#endif /* SUPERIO_ITE_COMMON_PRE_RAM_H */