Vladimir Serbinenko | b1ccccc | 2014-02-19 22:20:14 +0100 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2007-2009 coresystems GmbH |
| 5 | ## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org> |
| 6 | ## |
| 7 | ## This program is free software; you can redistribute it and/or |
| 8 | ## modify it under the terms of the GNU General Public License as |
| 9 | ## published by the Free Software Foundation; version 2 of |
| 10 | ## the License. |
| 11 | ## |
| 12 | ## This program is distributed in the hope that it will be useful, |
| 13 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | ## GNU General Public License for more details. |
| 16 | ## |
| 17 | ## You should have received a copy of the GNU General Public License |
| 18 | ## along with this program; if not, write to the Free Software |
| 19 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 20 | ## MA 02110-1301 USA |
| 21 | ## |
| 22 | |
| 23 | chip northbridge/intel/nehalem |
| 24 | |
| 25 | register "gpu_dp_b_hotplug" = "0x04" |
| 26 | register "gpu_dp_c_hotplug" = "0x04" |
| 27 | register "gpu_dp_d_hotplug" = "0x04" |
| 28 | |
| 29 | # Enable Panel as LVDS and configure power delays |
| 30 | register "gpu_panel_port_select" = "0" # LVDS |
| 31 | register "gpu_panel_power_cycle_delay" = "6" |
| 32 | register "gpu_panel_power_up_delay" = "300" |
| 33 | register "gpu_panel_power_down_delay" = "300" |
| 34 | register "gpu_panel_power_backlight_on_delay" = "3000" |
| 35 | register "gpu_panel_power_backlight_off_delay" = "3000" |
| 36 | register "gpu_cpu_backlight" = "0x58d" |
| 37 | register "gpu_pch_backlight" = "0x061a061a" |
Vladimir Serbinenko | a71bdc3 | 2014-08-30 00:35:39 +0200 | [diff] [blame^] | 38 | register "gfx.use_spread_spectrum_clock" = "0" |
| 39 | register "gfx.lvds_dual_channel" = "1" |
| 40 | register "gfx.link_frequency_270_mhz" = "1" |
| 41 | register "gfx.lvds_num_lanes" = "4" |
Vladimir Serbinenko | b1ccccc | 2014-02-19 22:20:14 +0100 | [diff] [blame] | 42 | |
| 43 | device cpu_cluster 0 on |
| 44 | chip cpu/intel/model_2065x |
| 45 | device lapic 0 on end |
| 46 | end |
| 47 | end |
| 48 | |
| 49 | device domain 0 on |
| 50 | device pci 00.0 on # Host bridge |
| 51 | subsystemid 0x1025 0x0379 |
| 52 | end |
| 53 | device pci 02.0 on # VGA controller |
| 54 | subsystemid 0x1025 0x0379 |
| 55 | end |
| 56 | chip southbridge/intel/ibexpeak |
| 57 | register "pirqa_routing" = "0x0b" |
| 58 | register "pirqb_routing" = "0x0b" |
| 59 | register "pirqc_routing" = "0x0b" |
| 60 | register "pirqd_routing" = "0x0b" |
| 61 | register "pirqe_routing" = "0x0b" |
| 62 | register "pirqf_routing" = "0x0b" |
| 63 | register "pirqg_routing" = "0x0b" |
| 64 | register "pirqh_routing" = "0x0b" |
| 65 | |
| 66 | # GPI routing |
| 67 | # 0 No effect (default) |
| 68 | # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) |
| 69 | # 2 SCI (if corresponding GPIO_EN bit is also set) |
| 70 | register "gpi7_routing" = "2" |
| 71 | register "gpi8_routing" = "2" |
| 72 | |
| 73 | register "sata_port_map" = "0x11" |
| 74 | |
| 75 | register "gpe0_en" = "0x01800046" |
| 76 | register "alt_gp_smi_en" = "0x0000" |
| 77 | register "gen1_dec" = "0x040069" |
| 78 | |
| 79 | device pci 1a.0 on # USB2 EHCI |
| 80 | subsystemid 0x1025 0x0379 |
| 81 | end |
| 82 | |
| 83 | device pci 1b.0 on # Audio Controller |
| 84 | subsystemid 0x1025 0x0379 |
| 85 | end |
| 86 | |
| 87 | device pci 1c.0 on end # PCIe Port #1 |
| 88 | device pci 1c.1 on end # PCIe Port #1 |
| 89 | |
| 90 | device pci 1d.0 on # USB2 EHCI |
| 91 | subsystemid 0x1025 0x0379 |
| 92 | end |
| 93 | device pci 1f.0 on # PCI-LPC bridge |
| 94 | subsystemid 0x1025 0x0379 |
| 95 | end |
| 96 | device pci 1f.2 on # IDE/SATA |
| 97 | subsystemid 0x1025 0x0379 |
| 98 | end |
| 99 | device pci 1f.3 on # SMBUS |
| 100 | subsystemid 0x1025 0x0379 |
| 101 | end |
| 102 | end |
| 103 | end |
| 104 | end |