| Joel Linn | a70493d | 2024-03-02 13:59:52 +0100 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <bootblock_common.h> |
| 4 | #include <device/pci_ops.h> |
| 5 | #include <superio/ite/common/ite.h> |
| 6 | #include <southbridge/intel/bd82x6x/pch.h> |
| 7 | #include <superio/hwm5_conf.h> |
| 8 | #include "common_defines.h" |
| 9 | #include "led.h" |
| 10 | |
| 11 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 12 | { 1, 6, 0 }, |
| 13 | { 1, 6, 0 }, |
| 14 | { 1, 6, 1 }, |
| 15 | { 1, 9, 1 }, |
| 16 | { 1, 10, 2 }, |
| 17 | { 1, 11, 2 }, |
| 18 | { 1, 6, 3 }, |
| 19 | { 1, 6, 3 }, |
| 20 | { 1, 6, 4 }, |
| 21 | { 1, 12, 4 }, |
| 22 | { 1, 6, 6 }, |
| 23 | { 1, 11, 5 }, |
| 24 | { 1, 6, 5 }, |
| 25 | { 1, 6, 6 }, |
| 26 | }; |
| 27 | |
| 28 | void bootblock_mainboard_early_init(void) |
| 29 | { |
| 30 | pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN); |
| 31 | |
| 32 | /* Early SuperIO setup */ |
| 33 | ite_conf_clkin(GPIO_DEV, ITE_UART_CLK_PREDIVIDE_24); |
| 34 | /* Clear when resuming from S3: */ |
| 35 | ite_disable_3vsbsw(GPIO_DEV); |
| 36 | ite_disable_pme_out(EC_DEV); |
| 37 | ite_ac_resume_southbridge(EC_DEV); |
| 38 | |
| 39 | set_power_led(LED_WHITE); |
| 40 | } |