blob: cbe5d860b0e7db3a04e64e4128809b31ab168e38 [file] [log] [blame]
Angel Ponsae593872020-04-04 18:50:57 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Marshall Dawson3edc9e22019-08-16 08:45:20 -06002
3#include <console/console.h>
4#include <device/device.h>
5#include <device/pci.h>
6#include <device/pci_ids.h>
7#include <device/pci_ops.h>
8#include "chip.h"
Raul E Rangel4c7e0d72020-05-07 15:14:09 -06009#include <soc/acp.h>
Marshall Dawson3edc9e22019-08-16 08:45:20 -060010#include <soc/acpi.h>
11#include <soc/pci_devs.h>
Marshall Dawson3edc9e22019-08-16 08:45:20 -060012#include <soc/southbridge.h>
13#include <amdblocks/acpimmio.h>
14#include <commonlib/helpers.h>
15
16static void enable(struct device *dev)
17{
18 const struct soc_amd_picasso_config *cfg;
19 const struct device *nb_dev = pcidev_path_on_root(GNB_DEVFN);
20 struct resource *res;
21 uintptr_t bar;
22
23 pci_dev_enable_resources(dev);
24
25 /* Set the proper I2S_PIN_CONFIG state */
26 if (!nb_dev || !nb_dev->chip_info)
27 return;
28
29 cfg = nb_dev->chip_info;
30
31 res = dev->resource_list;
32 if (!res || !res->base) {
33 printk(BIOS_ERR, "Error, unable to configure pin in %s\n", __func__);
34 return;
35 }
36
37 bar = (uintptr_t)res->base;
38 write32((void *)(bar + ACP_I2S_PIN_CONFIG), cfg->acp_pin_cfg);
39
40 if (cfg->acp_pin_cfg == I2S_PINS_I2S_TDM)
41 sb_clk_output_48Mhz(); /* Internal connection to I2S */
42}
43
Marshall Dawson3edc9e22019-08-16 08:45:20 -060044static struct device_operations acp_ops = {
45 .read_resources = pci_dev_read_resources,
46 .set_resources = pci_dev_set_resources,
47 .enable_resources = enable,
Angel Pons1fc0edd2020-05-31 00:03:28 +020048 .ops_pci = &pci_dev_ops_pci,
Marshall Dawson3edc9e22019-08-16 08:45:20 -060049};
50
51static const struct pci_driver acp_driver __pci_driver = {
52 .ops = &acp_ops,
53 .vendor = PCI_VENDOR_ID_AMD,
Furquan Shaikha1cd7eb2020-04-15 23:58:22 -070054 .device = PCI_DEVICE_ID_AMD_FAM17H_ACP,
Marshall Dawson3edc9e22019-08-16 08:45:20 -060055};