Lee Leahy | a5258cb | 2016-05-30 14:06:25 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2016 Intel Corporation. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
| 17 | #include <delay.h> |
| 18 | #include <device/device.h> |
| 19 | #include <device/i2c.h> |
| 20 | #include <device/pci.h> |
| 21 | #include <device/pci_ids.h> |
| 22 | #include <soc/i2c.h> |
| 23 | #include <soc/ramstage.h> |
| 24 | #include <soc/reg_access.h> |
| 25 | |
| 26 | static void i2c_disable(I2C_REGS *regs) |
| 27 | { |
| 28 | uint32_t status; |
| 29 | uint32_t timeout; |
| 30 | |
| 31 | /* Disable I2C controller */ |
| 32 | regs->ic_enable = 0; |
| 33 | |
| 34 | /* Wait for the enable bit to clear */ |
| 35 | timeout = 1 * 1000 * 1000; |
| 36 | status = regs->ic_enable_status; |
| 37 | while (status & IC_ENABLE_CONTROLLER) { |
| 38 | udelay(1); |
| 39 | if (--timeout == 0) |
| 40 | die("ERROR - I2C failed to disable!\n"); |
| 41 | status = regs->ic_enable_status; |
| 42 | } |
| 43 | |
| 44 | /* Clear any pending interrupts */ |
| 45 | status = regs->ic_clr_intr; |
| 46 | } |
| 47 | |
| 48 | int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count) |
| 49 | { |
| 50 | uint8_t *buffer; |
| 51 | int bytes_transferred; |
| 52 | uint8_t chip; |
| 53 | uint32_t cmd; |
| 54 | int length; |
| 55 | int read_length; |
| 56 | I2C_REGS *regs; |
| 57 | uint32_t status; |
| 58 | uint32_t timeout; |
| 59 | |
| 60 | regs = get_i2c_address(); |
| 61 | |
| 62 | /* Disable the I2C controller to get access to the registers */ |
| 63 | i2c_disable(regs); |
| 64 | |
| 65 | /* Set the slave address */ |
| 66 | ASSERT (count > 0); |
| 67 | ASSERT (segments != NULL); |
| 68 | ASSERT (segments->read == 0); |
| 69 | |
| 70 | /* Clear the start and stop detection */ |
| 71 | status = regs->ic_clr_start_det; |
| 72 | status = regs->ic_clr_stop_det; |
| 73 | |
| 74 | /* Set addressing mode to 7-bit and fast mode */ |
| 75 | cmd = regs->ic_con; |
| 76 | cmd &= ~(IC_CON_10B | IC_CON_SPEED); |
| 77 | cmd |= IC_CON_RESTART_EN | IC_CON_7B | IC_CON_SPEED_100_KHz |
| 78 | | IC_CON_MASTER_MODE; |
| 79 | regs->ic_con = cmd; |
| 80 | |
| 81 | /* Set the target chip address */ |
| 82 | chip = segments->chip; |
| 83 | regs->ic_tar = chip; |
| 84 | |
| 85 | /* Enable the I2C controller */ |
| 86 | regs->ic_enable = IC_ENABLE_CONTROLLER; |
| 87 | |
| 88 | /* Clear the interrupts */ |
| 89 | status = regs->ic_clr_rx_under; |
| 90 | status = regs->ic_clr_rx_over; |
| 91 | status = regs->ic_clr_tx_over; |
| 92 | status = regs->ic_clr_tx_abrt; |
| 93 | |
| 94 | /* Process each of the segments */ |
| 95 | bytes_transferred = 0; |
| 96 | read_length = 0; |
| 97 | buffer = NULL; |
| 98 | while (count-- > 0) { |
| 99 | buffer = segments->buf; |
| 100 | length = segments->len; |
| 101 | ASSERT (buffer != NULL); |
| 102 | ASSERT (length >= 1); |
| 103 | ASSERT (segments->chip = chip); |
| 104 | |
| 105 | if (segments->read) { |
| 106 | /* Place read commands into the FIFO */ |
| 107 | read_length = length; |
| 108 | while (length > 0) { |
| 109 | /* Send stop bit after last byte */ |
| 110 | cmd = IC_DATA_CMD_READ; |
| 111 | if ((count == 0) && (length == 1)) |
| 112 | cmd |= IC_DATA_CMD_STOP; |
| 113 | |
| 114 | /* Place read command in transmit FIFO */ |
| 115 | regs->ic_data_cmd = cmd; |
| 116 | length--; |
| 117 | } |
| 118 | } else { |
| 119 | /* Write the data into the FIFO */ |
| 120 | while (length > 0) { |
| 121 | /* End of the transaction? */ |
| 122 | cmd = IC_DATA_CMD_WRITE | *buffer++; |
| 123 | if ((count == 0) && (length == 1)) |
| 124 | cmd |= IC_DATA_CMD_STOP; |
| 125 | |
| 126 | /* Place a data byte into the FIFO */ |
| 127 | regs->ic_data_cmd = cmd; |
| 128 | length--; |
| 129 | bytes_transferred++; |
| 130 | } |
| 131 | } |
| 132 | segments++; |
| 133 | } |
| 134 | |
| 135 | /* Wait for the end of the transaction */ |
| 136 | timeout = 1 * 1000 * 1000; |
| 137 | do { |
| 138 | status = regs->ic_raw_intr_stat; |
| 139 | if (status & IC_INTR_STOP_DET) |
| 140 | break; |
| 141 | if ((status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER |
| 142 | | IC_INTR_TX_ABRT | IC_INTR_TX_OVER)) |
| 143 | || (timeout == 0)) { |
| 144 | if (timeout == 0) |
| 145 | printk (BIOS_ERR, |
| 146 | "ERROR - I2C stop bit not received!\n"); |
| 147 | if (status & IC_INTR_RX_OVER) |
| 148 | printk (BIOS_ERR, |
| 149 | "ERROR - I2C receive overrun!\n"); |
| 150 | if (status & IC_INTR_RX_UNDER) |
| 151 | printk (BIOS_ERR, |
| 152 | "ERROR - I2C receive underrun!\n"); |
| 153 | if (status & IC_INTR_TX_ABRT) |
| 154 | printk (BIOS_ERR, |
| 155 | "ERROR - I2C transmit abort!\n"); |
| 156 | if (status & IC_INTR_TX_OVER) |
| 157 | printk (BIOS_ERR, |
| 158 | "ERROR - I2C transmit overrun!\n"); |
| 159 | i2c_disable(regs); |
| 160 | return -1; |
| 161 | } |
| 162 | timeout--; |
| 163 | udelay(1); |
| 164 | } while(1); |
| 165 | |
| 166 | /* Finish reading the data bytes */ |
| 167 | while (read_length > 0) { |
| 168 | status = regs->ic_status; |
| 169 | *buffer++ = (UINT8)regs->ic_data_cmd; |
| 170 | read_length--; |
| 171 | bytes_transferred++; |
| 172 | status = regs->ic_status; |
| 173 | } |
| 174 | |
| 175 | return bytes_transferred; |
| 176 | } |