| Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Martin Roth | 5474eb1 | 2018-05-26 19:22:33 -0600 | [diff] [blame] | 2 | |
| Iru Cai | d7ee9dd | 2016-02-24 15:03:58 +0800 | [diff] [blame] | 3 | #ifndef NORTHBRIDGE_INTEL_I945_CHIP_H |
| 4 | #define NORTHBRIDGE_INTEL_I945_CHIP_H |
| 5 | |
| Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 6 | #include <drivers/intel/gma/i915.h> |
| 7 | |
| Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 8 | struct northbridge_intel_i945_config { |
| Arthur Heymans | 8e07900 | 2017-01-14 22:31:54 +0100 | [diff] [blame] | 9 | /* In units of 100us timer */ |
| 10 | /* Timings as defined in VESA Notebook Panel Standard */ |
| 11 | u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ |
| 12 | u16 gpu_panel_power_down_delay; /* T3 time sequence */ |
| 13 | u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ |
| 14 | u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ |
| 15 | /* In units of 0.1s */ |
| 16 | u8 gpu_panel_power_cycle_delay; |
| 17 | |
| Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 18 | u32 gpu_hotplug; |
| Arthur Heymans | 8e07900 | 2017-01-14 22:31:54 +0100 | [diff] [blame] | 19 | u32 pwm_freq; |
| Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 20 | int gpu_lvds_use_spread_spectrum_clock; |
| Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 21 | struct i915_gpu_controller_info gfx; |
| Arthur Heymans | 885c289 | 2016-10-03 17:16:48 +0200 | [diff] [blame] | 22 | int pci_mmio_size; |
| Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 23 | }; |
| Iru Cai | d7ee9dd | 2016-02-24 15:03:58 +0800 | [diff] [blame] | 24 | |
| 25 | #endif /* NORTHBRIDGE_INTEL_I945_CHIP_H */ |