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review.coreboot.org / coreboot / a5215c4eb3a4cbe0ef32257c4da2e5a6e0febdef / . / src / soc / intel / alderlake / acpi / xhci.asl
blob: 1c3bbbe2dafb19dc8eb4123e307fb378168502ca [file] [log] [blame]
Subrata Banik08089922020-10-03 13:02:06 +0530[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
2
Subrata Banik36ca7b32023-03-23 14:48:53 +0530[diff] [blame]3#include <intelblocks/xhci.h>
Subrata Banik08089922020-10-03 13:02:06 +0530[diff] [blame]4#include <soc/gpe.h>
5
Reka Normana5215c42023-09-22 15:26:54 +1000[diff] [blame^]6/* Include UWES method for enabling USB wake */
7#include <soc/intel/common/acpi/xhci_wake.asl>
Scott Chao40e1cce2023-02-21 11:34:35 +0800[diff] [blame]8
Subrata Banik08089922020-10-03 13:02:06 +0530[diff] [blame]9/* XHCI Controller 0:14.0 */
10
11Device (XHCI)
12{
13 Name (_ADR, 0x00140000)
14
15 Name (_PRW, Package () { GPE0_PME_B0, 3 })
16
Scott Chao40e1cce2023-02-21 11:34:35 +0800[diff] [blame]17 OperationRegion (XPRT, PCI_Config, 0x00, 0x100)
18 Field (XPRT, AnyAcc, NoLock, Preserve)
19 {
20 Offset (0x10),
21 , 16,
22 XMEM, 16, /* MEM_BASE */
23 }
24
25 Method (_DSW, 3)
26 {
27 UWES ((\U2WE & 0xFFF), PORTSCN_OFFSET, XMEM)
28 UWES ((\U3WE & 0x3F ), PORTSCXUSB3_OFFSET, XMEM)
29 }
30
Subrata Banik08089922020-10-03 13:02:06 +0530[diff] [blame]31 Name (_S3D, 3) /* D3 supported in S3 */
32 Name (_S0W, 3) /* D3 can wake device in S0 */
33 Name (_S3W, 3) /* D3 can wake system from S3 */
34
35 Method (_PS0, 0, Serialized)
36 {
37
38 }
39
40 Method (_PS3, 0, Serialized)
41 {
42
43 }
Michał Żygowskif422ed82022-04-20 12:52:51 +0200[diff] [blame]44#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
45 /* Root Hub for Alder Lake-P PCH */
46 Device (RHUB)
47 {
Felix Singer9df60d32022-12-26 09:43:07 +0100[diff] [blame]48 Name (_ADR, 0)
Subrata Banik08089922020-10-03 13:02:06 +0530[diff] [blame]49
Michał Żygowskif422ed82022-04-20 12:52:51 +0200[diff] [blame]50 /* USB2 */
51 Device (HS01) { Name (_ADR, 1) }
52 Device (HS02) { Name (_ADR, 2) }
53 Device (HS03) { Name (_ADR, 3) }
54 Device (HS04) { Name (_ADR, 4) }
55 Device (HS05) { Name (_ADR, 5) }
56 Device (HS06) { Name (_ADR, 6) }
57 Device (HS07) { Name (_ADR, 7) }
58 Device (HS08) { Name (_ADR, 8) }
59 Device (HS09) { Name (_ADR, 9) }
60 Device (HS10) { Name (_ADR, 10) }
61 Device (HS11) { Name (_ADR, 11) }
62 Device (HS12) { Name (_ADR, 12) }
63 Device (HS13) { Name (_ADR, 13) }
64 Device (HS14) { Name (_ADR, 14) }
65 /* USB3 */
66 Device (SS01) { Name (_ADR, 15) }
67 Device (SS02) { Name (_ADR, 16) }
68 Device (SS03) { Name (_ADR, 17) }
69 Device (SS04) { Name (_ADR, 18) }
70 Device (SS05) { Name (_ADR, 19) }
71 Device (SS06) { Name (_ADR, 20) }
72 Device (SS07) { Name (_ADR, 21) }
73 Device (SS08) { Name (_ADR, 22) }
74 Device (SS09) { Name (_ADR, 23) }
75 Device (SS10) { Name (_ADR, 24) }
76 }
77#else
Subrata Banik08089922020-10-03 13:02:06 +0530[diff] [blame]78 /* Root Hub for Alder Lake-P PCH */
79 Device (RHUB)
80 {
Felix Singer9df60d32022-12-26 09:43:07 +0100[diff] [blame]81 Name (_ADR, 0)
Subrata Banik08089922020-10-03 13:02:06 +0530[diff] [blame]82
83 /* USB2 */
84 Device (HS01) { Name (_ADR, 1) }
85 Device (HS02) { Name (_ADR, 2) }
86 Device (HS03) { Name (_ADR, 3) }
87 Device (HS04) { Name (_ADR, 4) }
88 Device (HS05) { Name (_ADR, 5) }
89 Device (HS06) { Name (_ADR, 6) }
90 Device (HS07) { Name (_ADR, 7) }
91 Device (HS08) { Name (_ADR, 8) }
92 Device (HS09) { Name (_ADR, 9) }
93 Device (HS10) { Name (_ADR, 10) }
94 /* USB3 */
Adam Mills9c4514b2022-08-10 15:49:00 +1000[diff] [blame]95 Device (SS01) { Name (_ADR, 13) }
96 Device (SS02) { Name (_ADR, 14) }
97 Device (SS03) { Name (_ADR, 15) }
98 Device (SS04) { Name (_ADR, 16) }
Subrata Banik08089922020-10-03 13:02:06 +0530[diff] [blame]99 }
Michał Żygowskif422ed82022-04-20 12:52:51 +0200[diff] [blame]100#endif
Subrata Banik08089922020-10-03 13:02:06 +0530[diff] [blame]101}