| Sven Schnelle | 72f35a6 | 2012-06-20 14:56:46 +0200 | [diff] [blame] | 1 | # |
| 2 | # This file is part of the coreboot project. |
| 3 | # |
| 4 | # Copyright (C) 2007-2008 coresystems GmbH |
| 5 | # |
| 6 | # This program is free software; you can redistribute it and/or |
| 7 | # modify it under the terms of the GNU General Public License as |
| 8 | # published by the Free Software Foundation; version 2 of |
| 9 | # the License. |
| 10 | # |
| 11 | # This program is distributed in the hope that it will be useful, |
| 12 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | # GNU General Public License for more details. |
| 15 | # |
| Sven Schnelle | 72f35a6 | 2012-06-20 14:56:46 +0200 | [diff] [blame] | 16 | |
| 17 | # ----------------------------------------------------------------- |
| 18 | entries |
| 19 | |
| Sven Schnelle | 72f35a6 | 2012-06-20 14:56:46 +0200 | [diff] [blame] | 20 | # ----------------------------------------------------------------- |
| 21 | # Status Register A |
| Sven Schnelle | 72f35a6 | 2012-06-20 14:56:46 +0200 | [diff] [blame] | 22 | # ----------------------------------------------------------------- |
| 23 | # Status Register B |
| Sven Schnelle | 72f35a6 | 2012-06-20 14:56:46 +0200 | [diff] [blame] | 24 | # ----------------------------------------------------------------- |
| 25 | # Status Register C |
| 26 | #96 4 r 0 status_c_rsvd |
| 27 | #100 1 r 0 uf_flag |
| 28 | #101 1 r 0 af_flag |
| 29 | #102 1 r 0 pf_flag |
| 30 | #103 1 r 0 irqf_flag |
| 31 | # ----------------------------------------------------------------- |
| 32 | # Status Register D |
| 33 | #104 7 r 0 status_d_rsvd |
| 34 | #111 1 r 0 valid_cmos_ram |
| 35 | # ----------------------------------------------------------------- |
| 36 | # Diagnostic Status Register |
| 37 | #112 8 r 0 diag_rsvd1 |
| 38 | |
| 39 | # ----------------------------------------------------------------- |
| 40 | 0 120 r 0 reserved_memory |
| 41 | #120 264 r 0 unused |
| 42 | |
| 43 | # ----------------------------------------------------------------- |
| 44 | # RTC_BOOT_BYTE (coreboot hardcoded) |
| 45 | 384 1 e 4 boot_option |
| Nico Huber | d23ee5d | 2016-08-11 22:45:55 +0200 | [diff] [blame] | 46 | 388 4 h 0 reboot_counter |
| Sven Schnelle | 72f35a6 | 2012-06-20 14:56:46 +0200 | [diff] [blame] | 47 | #390 2 r 0 unused? |
| 48 | |
| 49 | # ----------------------------------------------------------------- |
| 50 | # coreboot config options: console |
| 51 | 392 3 e 5 baud_rate |
| 52 | 395 4 e 6 debug_level |
| 53 | #399 1 r 0 unused |
| 54 | |
| 55 | # coreboot config options: cpu |
| 56 | 400 1 e 2 hyper_threading |
| 57 | #401 7 r 0 unused |
| 58 | |
| 59 | # coreboot config options: southbridge |
| 60 | 408 1 e 1 nmi |
| 61 | #409 2 e 7 power_on_after_fail |
| 62 | #411 5 r 0 unused |
| 63 | |
| 64 | # coreboot config options: bootloader |
| 65 | 416 512 s 0 boot_devices |
| 66 | 928 8 h 0 boot_default |
| 67 | 936 1 e 8 cmos_defaults_loaded |
| 68 | 937 1 e 1 lpt |
| 69 | #938 46 r 0 unused |
| 70 | |
| 71 | # coreboot config options: check sums |
| 72 | 984 16 h 0 check_sum |
| 73 | |
| 74 | # ----------------------------------------------------------------- |
| 75 | |
| 76 | enumerations |
| 77 | |
| 78 | #ID value text |
| 79 | 1 0 Disable |
| 80 | 1 1 Enable |
| 81 | 2 0 Enable |
| 82 | 2 1 Disable |
| 83 | 4 0 Fallback |
| 84 | 4 1 Normal |
| 85 | 5 0 115200 |
| 86 | 5 1 57600 |
| 87 | 5 2 38400 |
| 88 | 5 3 19200 |
| 89 | 5 4 9600 |
| 90 | 5 5 4800 |
| 91 | 5 6 2400 |
| 92 | 5 7 1200 |
| 93 | 6 1 Emergency |
| 94 | 6 2 Alert |
| 95 | 6 3 Critical |
| 96 | 6 4 Error |
| 97 | 6 5 Warning |
| 98 | 6 6 Notice |
| 99 | 6 7 Info |
| 100 | 6 8 Debug |
| 101 | 6 9 Spew |
| 102 | 7 0 Disable |
| 103 | 7 1 Enable |
| 104 | 7 2 Keep |
| 105 | 8 0 No |
| 106 | 8 1 Yes |
| 107 | 9 0 Secondary |
| 108 | 9 1 Primary |
| 109 | # ----------------------------------------------------------------- |
| 110 | checksums |
| 111 | |
| 112 | checksum 392 983 984 |