| Werner Zeh | c42a613 | 2015-02-12 12:40:15 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Siemens AG |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| Werner Zeh | c42a613 | 2015-02-12 12:40:15 +0100 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #ifndef PTN3460_H_ |
| 17 | #define PTN3460_H_ |
| 18 | |
| 19 | #include <delay.h> |
| Werner Zeh | c42a613 | 2015-02-12 12:40:15 +0100 | [diff] [blame] | 20 | #include "lcd_panel.h" |
| 21 | |
| 22 | #define PTN_SLAVE_ADR 0x20 |
| 23 | #define PTN_I2C_CONTROLER 0 |
| 24 | |
| 25 | #define PTN_EDID_OFF 0x00 |
| 26 | #define PTN_EDID_LEN 0x80 |
| 27 | #define PTN_CONFIG_OFF 0x80 |
| 28 | #define PTN_CONFIG_LEN 0x19 |
| 29 | #define PTN_FLASH_CFG_OFF 0xE8 |
| 30 | #define PTN_FLASH_CFG_LEN 0x04 |
| 31 | #define PTN_MAX_EDID_NUM 6 |
| 32 | |
| 33 | /* Define some error codes that can be used */ |
| 34 | #define PTN_NO_ERROR 0x00000000 |
| 35 | #define PTN_BUS_ERROR 0x10000000 |
| 36 | #define PTN_INVALID_EDID 0x20000000 |
| 37 | |
| 38 | struct ptn_3460_config{ |
| 39 | u8 dp_interface_ctrl; /* DiplayPort interface control */ |
| 40 | u8 lvds_interface_ctrl1; /* LVDS interface control register 1 */ |
| 41 | u8 lvds_interface_ctrl2; /* LVDS interface control register 2 */ |
| 42 | u8 lvds_interface_ctrl3; /* LVDS interface control register 3 */ |
| 43 | u8 edid_rom_emulation; /* select which EDID-block is emulated */ |
| 44 | u8 edid_rom_access_ctrl; /* select which EDID block to map to 0..0x7F */ |
| 45 | u8 pwm_min[3]; /* smallest PWM frequency for back light */ |
| 46 | u8 pwm_max[3]; /* biggest PWM frequency for back light */ |
| 47 | u8 fast_link_ctrl; /* Fast link training control register */ |
| 48 | u8 pin_cfg_ctrl1; /* Pin configuration control register 1 */ |
| 49 | u8 pin_cfg_ctrl2; /* Pin configuration control register 2 */ |
| 50 | u8 pwm_default; /* Default PWM bit count in DPCD register */ |
| 51 | u16 pwm_value; /* Current PWM bit count in DPCD register */ |
| 52 | u8 pwm_default_freq; /* Default PWM frequency in DPCD register */ |
| 53 | u8 t3_timing; /* Panel T3 timing value */ |
| 54 | u8 t12_timing; /* Panel T12 timing value */ |
| 55 | u8 backlight_ctrl; /* Back light control register */ |
| 56 | u8 t2_delay; /* Panel T2 delay */ |
| 57 | u8 t4_timing; /* Panel T4 timing value */ |
| 58 | u8 t5_delay; /* Panel T5 delay */ |
| 59 | }__attribute__((packed)); |
| 60 | |
| 61 | struct ptn_3460_flash{ |
| 62 | u8 cmd; /* Flash command (erase or erase and flash) */ |
| 63 | u16 magic; /* Magic number needed by the flash algorithm */ |
| 64 | u8 trigger; /* Trigger for starting flash operation */ |
| 65 | }__attribute__((packed)); |
| 66 | |
| 67 | |
| Werner Zeh | bf13d3f | 2016-04-25 12:24:17 +0200 | [diff] [blame] | 68 | int ptn3460_init(char *hwi_block); |
| Werner Zeh | c42a613 | 2015-02-12 12:40:15 +0100 | [diff] [blame] | 69 | int ptn3460_read_edid(u8 edid_num, u8 *data); |
| 70 | int ptn3460_write_edid(u8 edid_num, u8 *data); |
| 71 | int ptn_select_edid(u8 edid_num); |
| 72 | int ptn3460_flash_config(void); |
| 73 | #endif /* PTN3460_H_ */ |