Werner Zeh | fa6f861 | 2016-04-20 10:08:17 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2011 Google Inc. |
Werner Zeh | b2213ed | 2016-06-30 08:21:17 +0200 | [diff] [blame] | 6 | * Copyright (C) 2016 Siemens AG |
Werner Zeh | fa6f861 | 2016-04-20 10:08:17 +0200 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #include <types.h> |
| 19 | #include <string.h> |
| 20 | #include <device/device.h> |
Werner Zeh | fa6f861 | 2016-04-20 10:08:17 +0200 | [diff] [blame] | 21 | #include <device/pci_def.h> |
| 22 | #include <device/pci_ops.h> |
| 23 | #include <console/console.h> |
| 24 | #if CONFIG_VGA_ROM_RUN |
| 25 | #include <x86emu/x86emu.h> |
| 26 | #endif |
| 27 | #include <pc80/mc146818rtc.h> |
| 28 | #include <arch/acpi.h> |
| 29 | #include <arch/io.h> |
| 30 | #include <arch/interrupt.h> |
| 31 | #include <boot/coreboot_tables.h> |
Werner Zeh | b2213ed | 2016-06-30 08:21:17 +0200 | [diff] [blame] | 32 | #include <hwilib.h> |
| 33 | #include <i210.h> |
Werner Zeh | e1d6aa6 | 2016-07-06 11:59:10 +0200 | [diff] [blame] | 34 | #include <soc/pci_devs.h> |
Werner Zeh | a845f42 | 2016-07-07 07:10:50 +0200 | [diff] [blame] | 35 | #include <soc/irq.h> |
Werner Zeh | 9d18e33 | 2016-09-08 07:52:03 +0200 | [diff] [blame] | 36 | #include <soc/lpc.h> |
Werner Zeh | fa6f861 | 2016-04-20 10:08:17 +0200 | [diff] [blame] | 37 | |
Werner Zeh | b2213ed | 2016-06-30 08:21:17 +0200 | [diff] [blame] | 38 | #define MAX_PATH_DEPTH 12 |
| 39 | #define MAX_NUM_MAPPINGS 10 |
Werner Zeh | e1d6aa6 | 2016-07-06 11:59:10 +0200 | [diff] [blame] | 40 | |
| 41 | /* |
| 42 | * SPI Opcode Menu setup for SPIBAR lock down |
| 43 | * should support most common flash chips. |
| 44 | */ |
| 45 | #define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ |
| 46 | #define SPI_OPTYPE_0 0x01 /* Write, no address */ |
| 47 | |
| 48 | #define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ |
| 49 | #define SPI_OPTYPE_1 0x03 /* Write, address required */ |
| 50 | |
| 51 | #define SPI_OPMENU_2 0x03 /* READ: Read Data */ |
| 52 | #define SPI_OPTYPE_2 0x02 /* Read, address required */ |
| 53 | |
| 54 | #define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ |
| 55 | #define SPI_OPTYPE_3 0x00 /* Read, no address */ |
| 56 | |
| 57 | #define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ |
| 58 | #define SPI_OPTYPE_4 0x03 /* Write, address required */ |
| 59 | |
| 60 | #define SPI_OPMENU_5 0x9f /* RDID: Read ID */ |
| 61 | #define SPI_OPTYPE_5 0x00 /* Read, no address */ |
| 62 | |
| 63 | #define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ |
| 64 | #define SPI_OPTYPE_6 0x03 /* Write, address required */ |
| 65 | |
| 66 | #define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ |
| 67 | #define SPI_OPTYPE_7 0x02 /* Read, address required */ |
| 68 | |
| 69 | #define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ |
| 70 | (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) |
| 71 | #define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ |
| 72 | (SPI_OPMENU_1 << 8) | SPI_OPMENU_0) |
| 73 | |
| 74 | #define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ |
| 75 | (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ |
| 76 | (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ |
| 77 | (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) |
| 78 | |
| 79 | #define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ |
| 80 | |
| 81 | #define SPIBAR_OFFSET 0x3800 |
| 82 | #define SPI_REG_PREOP 0x94 |
| 83 | #define SPI_REG_OPTYPE 0x96 |
| 84 | #define SPI_REG_OPMENU_L 0x98 |
| 85 | #define SPI_REG_OPMENU_H 0x9c |
| 86 | |
Werner Zeh | fa6f861 | 2016-04-20 10:08:17 +0200 | [diff] [blame] | 87 | /* |
| 88 | * mainboard_enable is executed as first thing after enumerate_buses(). |
| 89 | * This is the earliest point to add customization. |
| 90 | */ |
| 91 | static void mainboard_enable(device_t dev) |
| 92 | { |
| 93 | |
| 94 | } |
Werner Zeh | e1d6aa6 | 2016-07-06 11:59:10 +0200 | [diff] [blame] | 95 | |
Werner Zeh | a845f42 | 2016-07-07 07:10:50 +0200 | [diff] [blame] | 96 | static void mainboard_init(void *chip_info) |
| 97 | { |
| 98 | uint8_t actl = 0; |
| 99 | device_t dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); |
| 100 | |
| 101 | /* Route SCI to IRQ 10 to free IRQ 9 slot. */ |
| 102 | actl = pci_read_config8(dev, ACPI_CNTL_OFFSET); |
| 103 | actl &= ~SCIS_MASK; |
| 104 | actl |= SCIS_IRQ10; |
| 105 | pci_write_config8(dev, ACPI_CNTL_OFFSET, actl); |
Werner Zeh | 9d18e33 | 2016-09-08 07:52:03 +0200 | [diff] [blame] | 106 | |
| 107 | /* Enable additional I/O decoding ranges on LPC for COM 3 and COM 4 */ |
| 108 | pci_write_config32(dev, LPC_GEN1_DEC, 0x1C02E9); |
| 109 | pci_write_config32(dev, LPC_GEN2_DEC, 0x1C03E9); |
Werner Zeh | a845f42 | 2016-07-07 07:10:50 +0200 | [diff] [blame] | 110 | } |
| 111 | |
Werner Zeh | e1d6aa6 | 2016-07-06 11:59:10 +0200 | [diff] [blame] | 112 | static void mainboard_final(void *chip_info) |
| 113 | { |
| 114 | void *spi_base = NULL; |
| 115 | uint32_t rcba = 0; |
| 116 | device_t dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); |
| 117 | |
| 118 | /* Get address of SPI controller. */ |
| 119 | rcba = (pci_read_config32(dev, 0xf0) & 0xffffc000); |
| 120 | if (!rcba) |
| 121 | return; |
| 122 | spi_base = (void *)(rcba + SPIBAR_OFFSET); |
| 123 | /* Setup OPCODE menu */ |
| 124 | write16((spi_base + SPI_REG_PREOP), SPI_OPPREFIX); |
| 125 | write16((spi_base + SPI_REG_OPTYPE), SPI_OPTYPE); |
| 126 | write32((spi_base + SPI_REG_OPMENU_L), SPI_OPMENU_LOWER); |
| 127 | write32((spi_base + SPI_REG_OPMENU_H), SPI_OPMENU_UPPER); |
| 128 | } |
| 129 | |
Werner Zeh | b2213ed | 2016-06-30 08:21:17 +0200 | [diff] [blame] | 130 | /** \brief This function can decide if a given MAC address is valid or not. |
| 131 | * Currently, addresses filled with 0xff or 0x00 are not valid. |
| 132 | * @param mac Buffer to the MAC address to check |
| 133 | * @return 0 if address is not valid, otherwise 1 |
| 134 | */ |
| 135 | static uint8_t is_mac_adr_valid(uint8_t mac[6]) |
| 136 | { |
| 137 | uint8_t buf[6]; |
| 138 | |
| 139 | memset(buf, 0, sizeof(buf)); |
| 140 | if (!memcmp(buf, mac, sizeof(buf))) |
| 141 | return 0; |
| 142 | memset(buf, 0xff, sizeof(buf)); |
| 143 | if (!memcmp(buf, mac, sizeof(buf))) |
| 144 | return 0; |
| 145 | return 1; |
| 146 | } |
| 147 | /** \brief This function will search for a MAC address which can be assigned |
| 148 | * to a MACPHY. |
| 149 | * @param dev pointer to PCI device |
| 150 | * @param mac buffer where to store the MAC address |
| 151 | * @return cb_err CB_ERR or CB_SUCCESS |
| 152 | */ |
| 153 | enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[6]) |
| 154 | { |
| 155 | struct bus *parent = dev->bus; |
| 156 | uint8_t buf[16], mapping[16], i = 0, chain_len = 0; |
| 157 | |
| 158 | memset(buf, 0, sizeof(buf)); |
| 159 | memset(mapping, 0, sizeof(mapping)); |
| 160 | |
| 161 | /* The first entry in the tree is the device itself. */ |
| 162 | buf[0] = dev->path.pci.devfn; |
| 163 | chain_len = 1; |
| 164 | for (i = 1; i < MAX_PATH_DEPTH && parent->dev->bus->subordinate; i++) { |
| 165 | buf[i] = parent->dev->path.pci.devfn; |
| 166 | chain_len++; |
| 167 | parent = parent->dev->bus; |
| 168 | } |
| 169 | if (i == MAX_PATH_DEPTH) { |
| 170 | /* The path is deeper than MAX_PATH_DEPTH devices, error. */ |
| 171 | printk(BIOS_ERR, "Too many bridges for %s\n", dev_path(dev)); |
| 172 | return CB_ERR; |
| 173 | } |
| 174 | /* Now construct the mapping based on the device chain starting from */ |
| 175 | /* root bridge device to the device itself. */ |
| 176 | mapping[0] = 1; |
| 177 | mapping[1] = chain_len; |
| 178 | for (i = 0; i < chain_len; i++) |
| 179 | mapping[i + 4] = buf[chain_len - i - 1]; |
| 180 | |
| 181 | /* Open main hwinfo block */ |
| 182 | if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) |
| 183 | return CB_ERR; |
| 184 | /* Now try to find a valid MAC address in hwinfo for this mapping.*/ |
| 185 | for (i = 0; i < MAX_NUM_MAPPINGS; i++) { |
| 186 | if ((hwilib_get_field(XMac1Mapping + i, buf, 16) == 16) && |
| 187 | !(memcmp(buf, mapping, chain_len + 4))) { |
| 188 | /* There is a matching mapping available, get MAC address. */ |
| 189 | if ((hwilib_get_field(XMac1 + i, mac, 6) == 6) && |
| 190 | (is_mac_adr_valid(mac))) { |
| 191 | return CB_SUCCESS; |
| 192 | } else { |
| 193 | return CB_ERR; |
| 194 | } |
| 195 | } else |
| 196 | continue; |
| 197 | } |
| 198 | /* No MAC address found for */ |
| 199 | return CB_ERR; |
| 200 | } |
Werner Zeh | fa6f861 | 2016-04-20 10:08:17 +0200 | [diff] [blame] | 201 | |
| 202 | struct chip_operations mainboard_ops = { |
| 203 | .enable_dev = mainboard_enable, |
Werner Zeh | a845f42 | 2016-07-07 07:10:50 +0200 | [diff] [blame] | 204 | .init = mainboard_init, |
Werner Zeh | e1d6aa6 | 2016-07-06 11:59:10 +0200 | [diff] [blame] | 205 | .final = mainboard_final |
Werner Zeh | fa6f861 | 2016-04-20 10:08:17 +0200 | [diff] [blame] | 206 | }; |