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review.coreboot.org / coreboot / a50ced2eba20a007fa5b486c251c252ad09868cf / . / src / mainboard / siemens / mc_apl1 / romstage.c
blob: 9dd42bcfec7f1330b30617b4a4227ce64aca829a [file] [log] [blame]
Mario Scheithauer092db952017-01-31 15:45:13 +0100[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2016 Google Inc.
Mario Scheithauer6abdbcd2017-02-06 13:03:52 +0100[diff] [blame]5 * Copyright (C) 2017 Siemens AG
Mario Scheithauer092db952017-01-31 15:45:13 +0100[diff] [blame]6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <string.h>
18#include <soc/romstage.h>
19#include <fsp/api.h>
20#include <FspmUpd.h>
21#include "brd_gpio.h"
22
23static const uint8_t Ch0_Bit_swizzling[] = {
Mario Scheithauer6abdbcd2017-02-06 13:03:52 +0100[diff] [blame]24 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
25 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
26 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
27 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
Mario Scheithauer092db952017-01-31 15:45:13 +0100[diff] [blame]28};
29static const uint8_t Ch1_Bit_swizzling[] = {
Mario Scheithauer6abdbcd2017-02-06 13:03:52 +0100[diff] [blame]30 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
31 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
32 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
33 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
Mario Scheithauer092db952017-01-31 15:45:13 +0100[diff] [blame]34};
35static const uint8_t Ch2_Bit_swizzling[] = {
Mario Scheithauer6abdbcd2017-02-06 13:03:52 +0100[diff] [blame]36 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
37 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
38 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
39 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
Mario Scheithauer092db952017-01-31 15:45:13 +0100[diff] [blame]40};
41static const uint8_t Ch3_Bit_swizzling[] = {
Mario Scheithauer6abdbcd2017-02-06 13:03:52 +0100[diff] [blame]42 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
43 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
44 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
45 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
Mario Scheithauer092db952017-01-31 15:45:13 +0100[diff] [blame]46};
47
48void mainboard_memory_init_params(FSPM_UPD *memupd)
49{
50 /* setup early gpio before memory */
51 gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
52
53 /* DRAM Config settings */
54 memupd->FspmConfig.Package = 0x1;
Mario Scheithauer6abdbcd2017-02-06 13:03:52 +0100[diff] [blame]55 memupd->FspmConfig.Profile = 0x19;
Mario Scheithauer092db952017-01-31 15:45:13 +0100[diff] [blame]56 memupd->FspmConfig.MemoryDown = 0x1;
Mario Scheithauer6abdbcd2017-02-06 13:03:52 +0100[diff] [blame]57 memupd->FspmConfig.DDR3LPageSize = 0x2;
Mario Scheithauer092db952017-01-31 15:45:13 +0100[diff] [blame]58 memupd->FspmConfig.DDR3LASR = 0x0;
Mario Scheithauer6abdbcd2017-02-06 13:03:52 +0100[diff] [blame]59 memupd->FspmConfig.ScramblerSupport = 0x0;
60 memupd->FspmConfig.ChannelHashMask = 0x0;
61 memupd->FspmConfig.SliceHashMask = 0x0;
62 memupd->FspmConfig.InterleavedMode = 0x0;
Mario Scheithauer092db952017-01-31 15:45:13 +0100[diff] [blame]63 memupd->FspmConfig.ChannelsSlicesEnable = 0x0;
Mario Scheithauer6abdbcd2017-02-06 13:03:52 +0100[diff] [blame]64 memupd->FspmConfig.MinRefRate2xEnable = 0x1;
Mario Scheithauer092db952017-01-31 15:45:13 +0100[diff] [blame]65 memupd->FspmConfig.DualRankSupportEnable = 0x1;
66 memupd->FspmConfig.RmtMode = 0x0;
Mario Scheithauer6abdbcd2017-02-06 13:03:52 +0100[diff] [blame]67 memupd->FspmConfig.MemorySizeLimit = 0x1000;
Mario Scheithauer092db952017-01-31 15:45:13 +0100[diff] [blame]68 memupd->FspmConfig.LowMemoryMaxValue = 0x0;
69 memupd->FspmConfig.DisableFastBoot = 0x0;
70 memupd->FspmConfig.HighMemoryMaxValue = 0x0;
71 memupd->FspmConfig.DIMM0SPDAddress = 0x0;
72 memupd->FspmConfig.DIMM1SPDAddress = 0x0;
Mario Scheithauer6abdbcd2017-02-06 13:03:52 +0100[diff] [blame]73 memupd->FspmConfig.Ch0_RankEnable = 0x1;
Mario Scheithauer092db952017-01-31 15:45:13 +0100[diff] [blame]74 memupd->FspmConfig.Ch0_DeviceWidth = 0x1;
Mario Scheithauer6abdbcd2017-02-06 13:03:52 +0100[diff] [blame]75 memupd->FspmConfig.Ch0_DramDensity = 0x0;
Mario Scheithauer092db952017-01-31 15:45:13 +0100[diff] [blame]76 memupd->FspmConfig.Ch0_Option = 0x3;
Mario Scheithauer6abdbcd2017-02-06 13:03:52 +0100[diff] [blame]77 memupd->FspmConfig.Ch0_OdtConfig = 0x1;
Mario Scheithauer092db952017-01-31 15:45:13 +0100[diff] [blame]78 memupd->FspmConfig.Ch0_TristateClk1 = 0x0;
79 memupd->FspmConfig.Ch0_Mode2N = 0x0;
80 memupd->FspmConfig.Ch0_OdtLevels = 0x0;
Mario Scheithauer6abdbcd2017-02-06 13:03:52 +0100[diff] [blame]81 memupd->FspmConfig.Ch1_RankEnable = 0x1;
Mario Scheithauer092db952017-01-31 15:45:13 +0100[diff] [blame]82 memupd->FspmConfig.Ch1_DeviceWidth = 0x1;
Mario Scheithauer6abdbcd2017-02-06 13:03:52 +0100[diff] [blame]83 memupd->FspmConfig.Ch1_DramDensity = 0x0;
Mario Scheithauer092db952017-01-31 15:45:13 +0100[diff] [blame]84 memupd->FspmConfig.Ch1_Option = 0x3;
Mario Scheithauer6abdbcd2017-02-06 13:03:52 +0100[diff] [blame]85 memupd->FspmConfig.Ch1_OdtConfig = 0x1;
Mario Scheithauer092db952017-01-31 15:45:13 +0100[diff] [blame]86 memupd->FspmConfig.Ch1_TristateClk1 = 0x0;
87 memupd->FspmConfig.Ch1_Mode2N = 0x0;
88 memupd->FspmConfig.Ch1_OdtLevels = 0x0;
Mario Scheithauer6abdbcd2017-02-06 13:03:52 +0100[diff] [blame]89 memupd->FspmConfig.Ch2_RankEnable = 0x0;
Mario Scheithauer092db952017-01-31 15:45:13 +0100[diff] [blame]90 memupd->FspmConfig.Ch2_DeviceWidth = 0x1;
Mario Scheithauer6abdbcd2017-02-06 13:03:52 +0100[diff] [blame]91 memupd->FspmConfig.Ch2_DramDensity = 0x0;
Mario Scheithauer092db952017-01-31 15:45:13 +0100[diff] [blame]92 memupd->FspmConfig.Ch2_Option = 0x3;
93 memupd->FspmConfig.Ch2_OdtConfig = 0x0;
94 memupd->FspmConfig.Ch2_TristateClk1 = 0x0;
95 memupd->FspmConfig.Ch2_Mode2N = 0x0;
96 memupd->FspmConfig.Ch2_OdtLevels = 0x0;
Mario Scheithauer6abdbcd2017-02-06 13:03:52 +0100[diff] [blame]97 memupd->FspmConfig.Ch3_RankEnable = 0x0;
Mario Scheithauer092db952017-01-31 15:45:13 +0100[diff] [blame]98 memupd->FspmConfig.Ch3_DeviceWidth = 0x1;
Mario Scheithauer6abdbcd2017-02-06 13:03:52 +0100[diff] [blame]99 memupd->FspmConfig.Ch3_DramDensity = 0x0;
Mario Scheithauer092db952017-01-31 15:45:13 +0100[diff] [blame]100 memupd->FspmConfig.Ch3_Option = 0x3;
101 memupd->FspmConfig.Ch3_OdtConfig = 0x0;
102 memupd->FspmConfig.Ch3_TristateClk1 = 0x0;
103 memupd->FspmConfig.Ch3_Mode2N = 0x0;
104 memupd->FspmConfig.Ch3_OdtLevels = 0x0;
Mario Scheithauer6abdbcd2017-02-06 13:03:52 +0100[diff] [blame]105 memupd->FspmConfig.RmtCheckRun = 0x3;
Mario Scheithauer092db952017-01-31 15:45:13 +0100[diff] [blame]106 memupd->FspmConfig.MrcDataSaving = 0x0;
Mario Scheithauer6abdbcd2017-02-06 13:03:52 +0100[diff] [blame]107 memupd->FspmConfig.MrcFastBoot = 0x1;
Mario Scheithauer092db952017-01-31 15:45:13 +0100[diff] [blame]108
109 memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling,
110 sizeof(Ch0_Bit_swizzling));
111 memcpy(memupd->FspmConfig.Ch1_Bit_swizzling, &Ch1_Bit_swizzling,
112 sizeof(Ch1_Bit_swizzling));
113 memcpy(memupd->FspmConfig.Ch2_Bit_swizzling, &Ch2_Bit_swizzling,
114 sizeof(Ch2_Bit_swizzling));
115 memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling,
116 sizeof(Ch3_Bit_swizzling));
117
Mario Scheithauer6abdbcd2017-02-06 13:03:52 +0100[diff] [blame]118 memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0xC8;
Mario Scheithauer092db952017-01-31 15:45:13 +0100[diff] [blame]119 memupd->FspmConfig.MsgLevelMask = 0x0;
120}