| Mario Scheithauer | 092db95 | 2017-01-31 15:45:13 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2016 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | DefinitionBlock( |
| 17 | "dsdt.aml", |
| 18 | "DSDT", |
| 19 | 0x05, // DSDT revision: ACPI v5.0 |
| 20 | "COREv4", // OEM id |
| 21 | "COREBOOT", // OEM table id |
| 22 | 0x20110725 // OEM revision |
| 23 | ) |
| 24 | { |
| 25 | /* global NVS and variables */ |
| 26 | #include <soc/intel/apollolake/acpi/globalnvs.asl> |
| 27 | |
| 28 | /* CPU */ |
| 29 | #include <soc/intel/apollolake/acpi/cpu.asl> |
| 30 | |
| 31 | Scope (\_SB) { |
| 32 | Device (PCI0) |
| 33 | { |
| 34 | #include <soc/intel/apollolake/acpi/northbridge.asl> |
| 35 | #include <soc/intel/apollolake/acpi/southbridge.asl> |
| 36 | #include <soc/intel/apollolake/acpi/pch_hda.asl> |
| 37 | } |
| 38 | } |
| 39 | |
| 40 | /* Chipset specific sleep states */ |
| 41 | #include <soc/intel/apollolake/acpi/sleepstates.asl> |
| 42 | } |