Mario Scheithauer | 092db95 | 2017-01-31 15:45:13 +0100 | [diff] [blame] | 1 | chip soc/intel/apollolake |
| 2 | |
| 3 | device cpu_cluster 0 on |
| 4 | device lapic 0 on end |
| 5 | end |
| 6 | |
Mario Scheithauer | 092db95 | 2017-01-31 15:45:13 +0100 | [diff] [blame] | 7 | # Disable unused clkreq of PCIe root ports |
Mario Scheithauer | 6abdbcd | 2017-02-06 13:03:52 +0100 | [diff] [blame] | 8 | register "pcie_rp0_clkreq_pin" = "3" # PCIe-PCI-Bridge |
Mario Scheithauer | 092db95 | 2017-01-31 15:45:13 +0100 | [diff] [blame] | 9 | register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" |
Mario Scheithauer | 6abdbcd | 2017-02-06 13:03:52 +0100 | [diff] [blame] | 10 | register "pcie_rp2_clkreq_pin" = "0" # MACPHY |
| 11 | register "pcie_rp3_clkreq_pin" = "1" # MACPHY |
Mario Scheithauer | 092db95 | 2017-01-31 15:45:13 +0100 | [diff] [blame] | 12 | register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" |
| 13 | register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" |
| 14 | |
Mario Scheithauer | 092db95 | 2017-01-31 15:45:13 +0100 | [diff] [blame] | 15 | device domain 0 on |
| 16 | device pci 00.0 on end # - Host Bridge |
Mario Scheithauer | 6abdbcd | 2017-02-06 13:03:52 +0100 | [diff] [blame] | 17 | device pci 00.1 off end # - DPTF |
| 18 | device pci 00.2 off end # - NPK |
| 19 | device pci 02.0 on end # - Gen - Display |
| 20 | device pci 03.0 off end # - Iunit |
Mario Scheithauer | 092db95 | 2017-01-31 15:45:13 +0100 | [diff] [blame] | 21 | device pci 0d.0 on end # - P2SB |
Mario Scheithauer | 6abdbcd | 2017-02-06 13:03:52 +0100 | [diff] [blame] | 22 | device pci 0d.1 off end # - PMC |
Mario Scheithauer | 092db95 | 2017-01-31 15:45:13 +0100 | [diff] [blame] | 23 | device pci 0d.2 on end # - SPI |
Mario Scheithauer | 6abdbcd | 2017-02-06 13:03:52 +0100 | [diff] [blame] | 24 | device pci 0d.3 off end # - Shared SRAM |
| 25 | device pci 0e.0 off end # - Audio |
| 26 | device pci 11.0 on end # - ISH |
| 27 | device pci 12.0 on end # - SATA |
| 28 | device pci 13.0 on end # - RP 2 - PCIe A 0 - MACPHY |
| 29 | device pci 13.1 on end # - RP 3 - PCIe A 1 - MACPHY |
| 30 | device pci 13.2 off end # - RP 4 - PCIe-A 2 |
| 31 | device pci 13.3 off end # - RP 5 - PCIe-A 3 |
| 32 | device pci 14.0 on end # - RP 0 - PCIe-B 0 - PCIe-PCI-Bridge |
| 33 | device pci 14.1 off end # - RP 1 - PCIe-B 1 |
Mario Scheithauer | 092db95 | 2017-01-31 15:45:13 +0100 | [diff] [blame] | 34 | device pci 15.0 on end # - XHCI |
Mario Scheithauer | 6abdbcd | 2017-02-06 13:03:52 +0100 | [diff] [blame] | 35 | device pci 15.1 on end # - XDCI |
| 36 | device pci 16.0 on end # - I2C 0 |
| 37 | device pci 16.1 off end # - I2C 1 |
| 38 | device pci 16.2 off end # - I2C 2 |
| 39 | device pci 16.3 off end # - I2C 3 |
| 40 | device pci 17.0 off end # - I2C 4 |
| 41 | device pci 17.1 off end # - I2C 5 |
Mario Scheithauer | 092db95 | 2017-01-31 15:45:13 +0100 | [diff] [blame] | 42 | device pci 17.2 off end # - I2C 6 |
Mario Scheithauer | 6abdbcd | 2017-02-06 13:03:52 +0100 | [diff] [blame] | 43 | device pci 17.3 on end # - I2C 7 |
Mario Scheithauer | 092db95 | 2017-01-31 15:45:13 +0100 | [diff] [blame] | 44 | device pci 18.0 on end # - UART 0 |
| 45 | device pci 18.1 on end # - UART 1 |
| 46 | device pci 18.2 on end # - UART 2 |
Mario Scheithauer | 6abdbcd | 2017-02-06 13:03:52 +0100 | [diff] [blame] | 47 | device pci 18.3 on end # - UART 3 |
| 48 | device pci 19.0 off end # - SPI 0 |
Mario Scheithauer | 092db95 | 2017-01-31 15:45:13 +0100 | [diff] [blame] | 49 | device pci 19.1 off end # - SPI 1 |
| 50 | device pci 19.2 off end # - SPI 2 |
Mario Scheithauer | 6abdbcd | 2017-02-06 13:03:52 +0100 | [diff] [blame] | 51 | device pci 1a.0 off end # - PWM |
Mario Scheithauer | 092db95 | 2017-01-31 15:45:13 +0100 | [diff] [blame] | 52 | device pci 1b.0 on end # - SDCARD |
| 53 | device pci 1c.0 on end # - eMMC |
Mario Scheithauer | 6abdbcd | 2017-02-06 13:03:52 +0100 | [diff] [blame] | 54 | device pci 1d.0 off end # - UFS |
Mario Scheithauer | 092db95 | 2017-01-31 15:45:13 +0100 | [diff] [blame] | 55 | device pci 1e.0 off end # - SDIO |
| 56 | device pci 1f.0 on end # - LPC |
| 57 | device pci 1f.1 on end # - SMBUS |
| 58 | end |
| 59 | end |