blob: 7d4ed00fe109cd9b000acc5ffeb8613f44674328 [file] [log] [blame]
Ronald G. Minnich66bea522016-10-25 19:11:07 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2015 Google Inc.
5 * Copyright 2016 Jonathan Neuschäfer <j.neuschaefer@gmx.net>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of
10 * the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17#include <boot_device.h>
18#include <symbols.h>
19
20/*
21 * _dram is the start of RAM. We currently need to load coreboot.rom into
22 * RAM. The actual "rom" code on the FPGAs is in a block ram.
23 */
24static const struct mem_region_device boot_dev =
25 MEM_REGION_DEV_RO_INIT(_dram, CONFIG_ROM_SIZE);
26
27const struct region_device *boot_device_ro(void)
28{
29 return &boot_dev.rdev;
30}