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review.coreboot.org / coreboot / a50ced2eba20a007fa5b486c251c252ad09868cf / . / src / mainboard / lenovo / x60 / irq_tables.c
blob: 01e1c29d055e824bc92b95b0a95637895b570488 [file] [log] [blame]
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000[diff] [blame]15 */
16
17#include <arch/pirq_routing.h>
18
Stefan Reinauera47bd912012-11-15 15:15:15 -0800[diff] [blame]19static const struct irq_routing_table intel_irq_routing_table = {
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000[diff] [blame]20 PIRQ_SIGNATURE, /* u32 signature */
21 PIRQ_VERSION, /* u16 version */
22 32 + 16 * 15, /* Max. number of devices on the bus */
23 0x00, /* Interrupt router bus */
24 (0x1f << 3) | 0x0, /* Interrupt router dev */
25 0, /* IRQs devoted exclusively to PCI usage */
26 0x8086, /* Vendor */
27 0x122e, /* Device */
28 0, /* Miniport */
29 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
30 0xf5, /* Checksum (has to be set to some value that
31 * would give 0 after the sum of all bytes
32 * for this structure (including checksum).
Elyes HAOUASf4df9d12016-09-23 17:57:38 +0200[diff] [blame]33 */
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000[diff] [blame]34 {
35 /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
36 {0x00, (0x02 << 3) | 0x0, {{0x00, 0xdef8}, {0x61, 0x1cf8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* VGA 0:02.0 */
37 {0x00, (0x1b << 3) | 0x0, {{0x00, 0xdef8}, {0x61, 0x1cf8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* HD Audio 0:1b.0 */
38 {0x00, (0x1c << 3) | 0x0, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.0 */
39 {0x00, (0x1c << 3) | 0x1, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.1 */
40 {0x00, (0x1c << 3) | 0x2, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.2 */
41 {0x00, (0x1c << 3) | 0x3, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.3 */
42 {0x00, (0x1d << 3) | 0x0, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.0 */
43 {0x00, (0x1d << 3) | 0x1, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.1 */
44 {0x00, (0x1d << 3) | 0x2, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.2 */
45 {0x00, (0x1d << 3) | 0x3, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.3 */
46 {0x00, (0x1e << 3) | 0x0, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* PCI 0:1e.0 */
47 {0x00, (0x1f << 3) | 0x0, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* LPC 0:1f.0 */
48 {0x00, (0x1f << 3) | 0x1, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* IDE 0:1f.1 */
49 {0x00, (0x1f << 3) | 0x2, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* SATA 0:1f.2 */
50 }
51};
52
53unsigned long write_pirq_routing_table(unsigned long addr)
54{
Stefan Reinauera47bd912012-11-15 15:15:15 -0800[diff] [blame]55 return copy_pirq_routing_table(addr, &intel_irq_routing_table);
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000[diff] [blame]56}