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review.coreboot.org / coreboot / a50ced2eba20a007fa5b486c251c252ad09868cf / . / src / mainboard / lenovo / x60 / gpio.c
blob: 04984435132b4916a7fe2cb8f04522d99aa8e984 [file] [log] [blame]
Arthur Heymans62902ca2016-11-29 14:13:43 +0100[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2016 Arthur Heymans <arthur@aheymans.xyz>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <southbridge/intel/common/gpio.h>
17static const struct pch_gpio_set1 pch_gpio_set1_mode = {
18 .gpio1 = GPIO_MODE_GPIO, /* HDD_PRESENCE# */
19 .gpio6 = GPIO_MODE_GPIO, /* Unknown (Pulled high by R215 to VCC3B) */
20 .gpio7 = GPIO_MODE_GPIO, /* BDC_PRESENCE# */
21 .gpio8 = GPIO_MODE_GPIO, /* H8_WAKE# */
22 .gpio9 = GPIO_MODE_GPIO, /* RTC_BAT_IN# */
23 .gpio10 = GPIO_MODE_GPIO, /* Unknown (Pulled high by R700 to VCC3M) */
24 .gpio12 = GPIO_MODE_GPIO, /* H8SCI# */
25 .gpio13 = GPIO_MODE_GPIO, /* SLICE_ON_3M# */
26 .gpio14 = GPIO_MODE_GPIO, /* Unknown (Pulled high by R321 to VCC3) */
27 .gpio15 = GPIO_MODE_GPIO, /* Unknown (Pulled high by R258 to VCC3) */
28 .gpio22 = GPIO_MODE_GPIO, /* FWH_WP# */
29 .gpio24 = GPIO_MODE_GPIO,
30 .gpio25 = GPIO_MODE_GPIO, /* MDC_KILL# */
31 .gpio26 = GPIO_MODE_GPIO,
32 .gpio27 = GPIO_MODE_GPIO,
33 .gpio28 = GPIO_MODE_GPIO,
34};
35
36static const struct pch_gpio_set1 pch_gpio_set1_direction = {
37 .gpio1 = GPIO_DIR_INPUT,
38 .gpio6 = GPIO_DIR_INPUT,
39 .gpio7 = GPIO_DIR_INPUT,
40 .gpio8 = GPIO_DIR_INPUT,
41 .gpio9 = GPIO_DIR_INPUT,
42 .gpio10 = GPIO_DIR_INPUT,
43 .gpio12 = GPIO_DIR_INPUT,
44 .gpio13 = GPIO_DIR_INPUT,
45 .gpio14 = GPIO_DIR_INPUT,
46 .gpio15 = GPIO_DIR_INPUT,
47 .gpio22 = GPIO_DIR_INPUT,
48 .gpio24 = GPIO_DIR_OUTPUT,
49 .gpio25 = GPIO_DIR_OUTPUT,
50 .gpio26 = GPIO_DIR_OUTPUT,
51 .gpio27 = GPIO_DIR_OUTPUT,
52 .gpio28 = GPIO_DIR_OUTPUT,
53};
54
55static const struct pch_gpio_set1 pch_gpio_set1_level = {
56 .gpio24 = GPIO_LEVEL_HIGH,
57 .gpio25 = GPIO_LEVEL_HIGH,
58 .gpio26 = GPIO_LEVEL_LOW,
59 .gpio27 = GPIO_LEVEL_HIGH,
60 .gpio28 = GPIO_LEVEL_HIGH,
61};
62
63static const struct pch_gpio_set1 pch_gpio_set1_invert = {
64 .gpio1 = GPIO_INVERT,
65 .gpio6 = GPIO_INVERT,
66 .gpio7 = GPIO_INVERT,
67 .gpio8 = GPIO_INVERT,
68 .gpio12 = GPIO_INVERT,
69 .gpio13 = GPIO_INVERT,
70};
71
72static const struct pch_gpio_set1 pch_gpio_set1_blink = {
73};
74
75static const struct pch_gpio_set2 pch_gpio_set2_mode = {
76 .gpio33 = GPIO_MODE_GPIO, /* HDD_PRESENCE_2# */
77 .gpio36 = GPIO_MODE_GPIO, /* PLANARID0 */
78 .gpio37 = GPIO_MODE_GPIO, /* PLANARID1 */
79 .gpio38 = GPIO_MODE_GPIO, /* PLANARID2 */
80 .gpio39 = GPIO_MODE_GPIO, /* PLANARID3 */
81 .gpio48 = GPIO_MODE_GPIO, /* FWH_TBL# */
82};
83
84static const struct pch_gpio_set2 pch_gpio_set2_direction = {
85 .gpio33 = GPIO_DIR_OUTPUT,
86 .gpio36 = GPIO_DIR_INPUT,
87 .gpio37 = GPIO_DIR_INPUT,
88 .gpio38 = GPIO_DIR_INPUT,
89 .gpio39 = GPIO_DIR_INPUT,
90 .gpio48 = GPIO_DIR_OUTPUT,
91};
92
93static const struct pch_gpio_set2 pch_gpio_set2_level = {
94 .gpio33 = GPIO_LEVEL_HIGH,
95 .gpio48 = GPIO_LEVEL_HIGH,
96};
97
98const struct pch_gpio_map mainboard_gpio_map = {
99 .set1 = {
100 .mode = &pch_gpio_set1_mode,
101 .direction = &pch_gpio_set1_direction,
102 .level = &pch_gpio_set1_level,
103 .blink = &pch_gpio_set1_blink,
104 .invert = &pch_gpio_set1_invert,
105 },
106 .set2 = {
107 .mode = &pch_gpio_set2_mode,
108 .direction = &pch_gpio_set2_direction,
109 .level = &pch_gpio_set2_level,
110 },
111};