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Vladimir Serbinenkoe7e95022014-01-12 15:26:15 +01001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2010 coresystems GmbH
5 * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
Vladimir Serbinenkob2939f72014-01-22 17:12:35 +01006 * Copyright (C) 2014 Vladimir Serbinenko
Vladimir Serbinenkoe7e95022014-01-12 15:26:15 +01007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Vladimir Serbinenkoe7e95022014-01-12 15:26:15 +010016 */
17
18#include <stdint.h>
19#include <string.h>
20#include <lib.h>
21#include <timestamp.h>
22#include <arch/byteorder.h>
23#include <arch/io.h>
24#include <device/pci_def.h>
25#include <device/pnp_def.h>
26#include <cpu/x86/lapic.h>
27#include <pc80/mc146818rtc.h>
Kyösti Mälkki6722f8d2014-06-16 09:14:49 +030028#include <arch/acpi.h>
Vladimir Serbinenkoe7e95022014-01-12 15:26:15 +010029#include <cbmem.h>
30#include <console/console.h>
Edward O'Callaghan77757c22015-01-04 21:33:39 +110031#include <northbridge/intel/sandybridge/sandybridge.h>
32#include <northbridge/intel/sandybridge/raminit_native.h>
33#include <southbridge/intel/bd82x6x/pch.h>
Patrick Rudolphe8e66f42016-02-06 17:42:42 +010034#include <southbridge/intel/common/gpio.h>
Vladimir Serbinenkoe7e95022014-01-12 15:26:15 +010035#include <arch/cpu.h>
Vladimir Serbinenkoe7e95022014-01-12 15:26:15 +010036#include <cpu/x86/msr.h>
Vladimir Serbinenkoe7e95022014-01-12 15:26:15 +010037#include <cbfs.h>
38
Vladimir Serbinenkofa1d6882014-10-19 02:50:45 +020039void pch_enable_lpc(void)
Vladimir Serbinenkoe7e95022014-01-12 15:26:15 +010040{
41 /* X230 EC Decode Range Port60/64, Port62/66 */
42 /* Enable EC, PS/2 Keyboard/Mouse */
43 pci_write_config16(PCH_LPC_DEV, LPC_EN,
44 CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
45 COMA_LPC_EN);
46
47 pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
48 pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
49 pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
50
51 pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
52
53 pci_write_config32(PCH_LPC_DEV, 0xac,
54 0x80010000);
55}
56
Vladimir Serbinenkofa1d6882014-10-19 02:50:45 +020057void rcba_config(void)
Vladimir Serbinenkoe7e95022014-01-12 15:26:15 +010058{
Vladimir Serbinenkoe7e95022014-01-12 15:26:15 +010059 /* Disable unused devices (board specific) */
60 RCBA32(FD) = 0x17f81fe3;
61 RCBA32(BUC) = 0;
62}
63
Vladimir Serbinenkofa1d6882014-10-19 02:50:45 +020064const struct southbridge_usb_port mainboard_usb_ports[] = {
65 { 1, 0, 0 }, /* P0 (left, fan side), OC 0 */
66 { 1, 0, 1 }, /* P1 (left touchpad side), OC 1 */
67 { 1, 1, 3 }, /* P2: dock, OC 3 */
68 { 1, 1, -1 }, /* P3: wwan, no OC */
69 { 1, 1, -1 }, /* P4: Wacom tablet on X230t, otherwise empty */
70 { 1, 1, -1 }, /* P5: Expresscard, no OC */
71 { 0, 0, -1 }, /* P6: Empty */
72 { 1, 2, -1 }, /* P7: dock, no OC */
73 { 1, 0, -1 },
74 { 1, 2, 5 }, /* P9: Right (EHCI debug), OC 5 */
75 { 1, 1, -1 }, /* P10: fingerprint reader, no OC */
76 { 1, 1, -1 }, /* P11: bluetooth, no OC. */
77 { 1, 1, -1 }, /* P12: wlan, no OC */
78 { 1, 1, -1 }, /* P13: webcam, no OC */
79};
Vladimir Serbinenkoe7e95022014-01-12 15:26:15 +010080
Kyösti Mälkkie258b9a2016-11-18 19:59:23 +020081void mainboard_get_spd(spd_raw_data *spd, bool id_only) {
82 read_spd (&spd[0], 0x50, id_only);
83 read_spd (&spd[2], 0x51, id_only);
Vladimir Serbinenkoe7e95022014-01-12 15:26:15 +010084}
Vladimir Serbinenko609bd942016-01-31 14:00:54 +010085
86void mainboard_early_init(int s3resume) {
87}
Vladimir Serbinenkoffbb3c02016-02-10 01:36:25 +010088
89void mainboard_config_superio(void)
90{
91}