Sven Schnelle | d8129f9 | 2011-04-20 09:12:17 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Sven Schnelle | d8129f9 | 2011-04-20 09:12:17 +0000 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | // __PRE_RAM__ means: use "unsigned" for device, not a struct. |
| 19 | |
| 20 | #include <stdint.h> |
| 21 | #include <string.h> |
| 22 | #include <arch/io.h> |
Sven Schnelle | d8129f9 | 2011-04-20 09:12:17 +0000 | [diff] [blame] | 23 | #include <device/pci_def.h> |
| 24 | #include <device/pnp_def.h> |
| 25 | #include <cpu/x86/lapic.h> |
| 26 | #include <lib.h> |
Kyösti Mälkki | 12d681b | 2014-06-14 18:51:34 +0300 | [diff] [blame] | 27 | #include <arch/acpi.h> |
Paul Menzel | ac6ea04 | 2013-04-29 23:21:07 +0200 | [diff] [blame] | 28 | #include <cbmem.h> |
Nico Huber | 44c392f | 2013-05-26 19:37:47 +0200 | [diff] [blame] | 29 | #include <timestamp.h> |
Sven Schnelle | d8129f9 | 2011-04-20 09:12:17 +0000 | [diff] [blame] | 30 | #include <pc80/mc146818rtc.h> |
| 31 | #include <console/console.h> |
Sven Schnelle | d8129f9 | 2011-04-20 09:12:17 +0000 | [diff] [blame] | 32 | #include <cpu/x86/bist.h> |
Kyösti Mälkki | 15fa992 | 2016-06-17 10:00:28 +0300 | [diff] [blame] | 33 | #include <cpu/intel/romstage.h> |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 34 | #include <halt.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 35 | #include <northbridge/intel/i945/i945.h> |
| 36 | #include <northbridge/intel/i945/raminit.h> |
| 37 | #include <southbridge/intel/i82801gx/i82801gx.h> |
Arthur Heymans | 62902ca | 2016-11-29 14:13:43 +0100 | [diff] [blame] | 38 | #include <southbridge/intel/common/gpio.h> |
Sven Schnelle | d8129f9 | 2011-04-20 09:12:17 +0000 | [diff] [blame] | 39 | #include "dock.h" |
| 40 | |
Sven Schnelle | d8129f9 | 2011-04-20 09:12:17 +0000 | [diff] [blame] | 41 | static void ich7_enable_lpc(void) |
| 42 | { |
| 43 | // Enable Serial IRQ |
| 44 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); |
| 45 | // decode range |
| 46 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0210); |
| 47 | // decode range |
| 48 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1f0d); |
| 49 | |
| 50 | /* range 0x1600 - 0x167f */ |
| 51 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x1601); |
| 52 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x007c); |
| 53 | |
| 54 | /* range 0x15e0 - 0x10ef */ |
| 55 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x15e1); |
| 56 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x000c); |
| 57 | |
| 58 | /* range 0x1680 - 0x169f */ |
| 59 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x1681); |
| 60 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x001c); |
| 61 | } |
| 62 | |
| 63 | static void early_superio_config(void) |
| 64 | { |
| 65 | int timeout = 100000; |
Antonello Dettori | ec4555b | 2016-09-02 09:12:20 +0200 | [diff] [blame] | 66 | pnp_devfn_t dev = PNP_DEV(0x2e, 3); |
Sven Schnelle | d8129f9 | 2011-04-20 09:12:17 +0000 | [diff] [blame] | 67 | |
| 68 | pnp_write_config(dev, 0x29, 0xa0); |
| 69 | |
| 70 | while(!(pnp_read_config(dev, 0x29) & 0x10) && timeout--) |
| 71 | udelay(1000); |
| 72 | |
| 73 | /* Enable COM1 */ |
| 74 | pnp_set_logical_device(dev); |
| 75 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); |
| 76 | pnp_set_enable(dev, 1); |
| 77 | } |
| 78 | |
| 79 | static void rcba_config(void) |
| 80 | { |
| 81 | /* Set up virtual channel 0 */ |
| 82 | RCBA32(0x0014) = 0x80000001; |
| 83 | RCBA32(0x001c) = 0x03128010; |
| 84 | |
| 85 | /* Device 1f interrupt pin register */ |
| 86 | RCBA32(0x3100) = 0x00001230; |
| 87 | RCBA32(0x3108) = 0x40004321; |
| 88 | |
| 89 | /* PCIe Interrupts */ |
| 90 | RCBA32(0x310c) = 0x00004321; |
| 91 | /* HD Audio Interrupt */ |
| 92 | RCBA32(0x3110) = 0x00000002; |
| 93 | |
| 94 | /* dev irq route register */ |
| 95 | RCBA16(0x3140) = 0x1007; |
| 96 | RCBA16(0x3142) = 0x0076; |
| 97 | RCBA16(0x3144) = 0x3210; |
| 98 | RCBA16(0x3146) = 0x7654; |
| 99 | RCBA16(0x3148) = 0x0010; |
| 100 | |
| 101 | /* Enable IOAPIC */ |
| 102 | RCBA8(0x31ff) = 0x03; |
| 103 | |
Sven Schnelle | d8129f9 | 2011-04-20 09:12:17 +0000 | [diff] [blame] | 104 | /* Disable unused devices */ |
| 105 | RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD; |
| 106 | RCBA32(0x3418) |= (1 << 0); // Required. |
| 107 | |
| 108 | /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ |
| 109 | RCBA32(0x1e84) = 0x00020001; |
| 110 | RCBA32(0x1e80) = 0x0000fe01; |
| 111 | |
| 112 | /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ |
| 113 | RCBA32(0x1e9c) = 0x000200f0; |
| 114 | RCBA32(0x1e98) = 0x000c0801; |
| 115 | } |
| 116 | |
| 117 | static void early_ich7_init(void) |
| 118 | { |
| 119 | uint8_t reg8; |
| 120 | uint32_t reg32; |
| 121 | |
| 122 | // program secondary mlt XXX byte? |
| 123 | pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); |
| 124 | |
| 125 | // reset rtc power status |
| 126 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); |
| 127 | reg8 &= ~(1 << 2); |
| 128 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); |
| 129 | |
| 130 | // usb transient disconnect |
| 131 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); |
| 132 | reg8 |= (3 << 0); |
| 133 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); |
| 134 | |
| 135 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); |
| 136 | reg32 |= (1 << 29) | (1 << 17); |
| 137 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); |
| 138 | |
| 139 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); |
| 140 | reg32 |= (1 << 31) | (1 << 27); |
| 141 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); |
| 142 | |
| 143 | RCBA32(0x0088) = 0x0011d000; |
| 144 | RCBA16(0x01fc) = 0x060f; |
| 145 | RCBA32(0x01f4) = 0x86000040; |
| 146 | RCBA32(0x0214) = 0x10030549; |
| 147 | RCBA32(0x0218) = 0x00020504; |
| 148 | RCBA8(0x0220) = 0xc5; |
| 149 | reg32 = RCBA32(0x3410); |
| 150 | reg32 |= (1 << 6); |
| 151 | RCBA32(0x3410) = reg32; |
| 152 | reg32 = RCBA32(0x3430); |
| 153 | reg32 &= ~(3 << 0); |
| 154 | reg32 |= (1 << 0); |
| 155 | RCBA32(0x3430) = reg32; |
| 156 | RCBA32(0x3418) |= (1 << 0); |
| 157 | RCBA16(0x0200) = 0x2008; |
| 158 | RCBA8(0x2027) = 0x0d; |
| 159 | RCBA16(0x3e08) |= (1 << 7); |
| 160 | RCBA16(0x3e48) |= (1 << 7); |
| 161 | RCBA32(0x3e0e) |= (1 << 7); |
| 162 | RCBA32(0x3e4e) |= (1 << 7); |
| 163 | |
| 164 | // next step only on ich7m b0 and later: |
| 165 | reg32 = RCBA32(0x2034); |
| 166 | reg32 &= ~(0x0f << 16); |
| 167 | reg32 |= (5 << 16); |
| 168 | RCBA32(0x2034) = reg32; |
| 169 | } |
| 170 | |
Kyösti Mälkki | 15fa992 | 2016-06-17 10:00:28 +0300 | [diff] [blame] | 171 | void mainboard_romstage_entry(unsigned long bist) |
Sven Schnelle | d8129f9 | 2011-04-20 09:12:17 +0000 | [diff] [blame] | 172 | { |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 173 | int s3resume = 0; |
| 174 | int dock_err; |
Sven Schnelle | d8129f9 | 2011-04-20 09:12:17 +0000 | [diff] [blame] | 175 | const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 }; |
| 176 | |
Nico Huber | 44c392f | 2013-05-26 19:37:47 +0200 | [diff] [blame] | 177 | |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 178 | timestamp_init(get_initial_timestamp()); |
| 179 | timestamp_add_now(TS_START_ROMSTAGE); |
Nico Huber | 44c392f | 2013-05-26 19:37:47 +0200 | [diff] [blame] | 180 | |
Sven Schnelle | d8129f9 | 2011-04-20 09:12:17 +0000 | [diff] [blame] | 181 | if (bist == 0) |
| 182 | enable_lapic(); |
| 183 | |
| 184 | /* Force PCIRST# */ |
| 185 | pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); |
| 186 | udelay(200 * 1000); |
| 187 | pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); |
| 188 | |
| 189 | ich7_enable_lpc(); |
| 190 | |
Sven Schnelle | b538110 | 2011-10-15 17:31:01 +0200 | [diff] [blame] | 191 | /* We want early GPIO setup, to be able to detect legacy I/O module */ |
| 192 | pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); |
| 193 | /* Enable GPIOs */ |
| 194 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); |
Arthur Heymans | 62902ca | 2016-11-29 14:13:43 +0100 | [diff] [blame] | 195 | setup_pch_gpios(&mainboard_gpio_map); |
Sven Schnelle | d8129f9 | 2011-04-20 09:12:17 +0000 | [diff] [blame] | 196 | |
Sven Schnelle | b538110 | 2011-10-15 17:31:01 +0200 | [diff] [blame] | 197 | dock_err = dlpc_init(); |
| 198 | |
| 199 | /* We prefer Legacy I/O module over docking */ |
| 200 | if (legacy_io_present()) { |
| 201 | legacy_io_init(); |
| 202 | early_superio_config(); |
| 203 | } else if (!dock_err && dock_present()) { |
Sven Schnelle | d8129f9 | 2011-04-20 09:12:17 +0000 | [diff] [blame] | 204 | dock_connect(); |
| 205 | early_superio_config(); |
Sven Schnelle | d8129f9 | 2011-04-20 09:12:17 +0000 | [diff] [blame] | 206 | } |
| 207 | |
Sven Schnelle | b538110 | 2011-10-15 17:31:01 +0200 | [diff] [blame] | 208 | /* Setup the console */ |
Sven Schnelle | d8129f9 | 2011-04-20 09:12:17 +0000 | [diff] [blame] | 209 | console_init(); |
| 210 | |
| 211 | /* Halt if there was a built in self test failure */ |
| 212 | report_bist_failure(bist); |
| 213 | |
| 214 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
| 215 | printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); |
| 216 | outb(0x6, 0xcf9); |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 217 | halt(); |
Sven Schnelle | d8129f9 | 2011-04-20 09:12:17 +0000 | [diff] [blame] | 218 | } |
| 219 | |
| 220 | /* Perform some early chipset initialization required |
| 221 | * before RAM initialization can work |
| 222 | */ |
| 223 | i945_early_initialization(); |
| 224 | |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 225 | s3resume = southbridge_detect_s3_resume(); |
Sven Schnelle | d8129f9 | 2011-04-20 09:12:17 +0000 | [diff] [blame] | 226 | |
| 227 | /* Enable SPD ROMs and DDR-II DRAM */ |
| 228 | enable_smbus(); |
| 229 | |
| 230 | #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 |
| 231 | dump_spd_registers(); |
| 232 | #endif |
| 233 | |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 234 | timestamp_add_now(TS_BEFORE_INITRAM); |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 235 | sdram_initialize(s3resume ? 2 : 0, spd_addrmap); |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 236 | timestamp_add_now(TS_AFTER_INITRAM); |
Sven Schnelle | d8129f9 | 2011-04-20 09:12:17 +0000 | [diff] [blame] | 237 | |
| 238 | /* Perform some initialization that must run before stage2 */ |
| 239 | early_ich7_init(); |
| 240 | |
| 241 | /* This should probably go away. Until now it is required |
| 242 | * and mainboard specific |
| 243 | */ |
| 244 | rcba_config(); |
| 245 | |
| 246 | /* Chipset Errata! */ |
| 247 | fixup_i945_errata(); |
| 248 | |
| 249 | /* Initialize the internal PCIe links before we go into stage2 */ |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 250 | i945_late_initialization(s3resume); |
Sven Schnelle | d8129f9 | 2011-04-20 09:12:17 +0000 | [diff] [blame] | 251 | } |