| Nicolas Reinecke | 2bffa8a | 2015-10-01 15:34:37 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * Copyright (C) 2014 Vladimir Serbinenko |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #include <arch/io.h> |
| 19 | #include <northbridge/intel/sandybridge/raminit_native.h> |
| 20 | #include <southbridge/intel/bd82x6x/pch.h> |
| 21 | |
| 22 | void pch_enable_lpc(void) |
| 23 | { |
| 24 | /* EC Decode Range Port60/64, Port62/66 */ |
| 25 | /* Enable EC, PS/2 Keyboard/Mouse */ |
| 26 | pci_write_config16(PCH_LPC_DEV, LPC_EN, |
| 27 | CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | |
| 28 | COMA_LPC_EN); |
| 29 | |
| 30 | pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); |
| 31 | pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); |
| 32 | pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); |
| 33 | |
| 34 | pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); |
| 35 | |
| 36 | pci_write_config32(PCH_LPC_DEV, 0xac, 0x80010000); |
| 37 | } |
| 38 | |
| 39 | void rcba_config(void) |
| 40 | { |
| 41 | /* Disable unused devices (board specific) */ |
| 42 | RCBA32(FD) = 0x1ea51fe3; |
| 43 | RCBA32(BUC) = 0; |
| 44 | } |
| 45 | // OC3 set in bios to port 2-7, OC7 set in bios to port 10-13 |
| 46 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 47 | { 1, 1, 0 }, /* P0: system port 4, OC0 */ |
| 48 | { 1, 1, 1 }, /* P1: system port 2 (EHCI debug), OC 1 */ |
| 49 | { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */ |
| 50 | { 1, 0, -1 }, /* P3: WWAN, no OC */ |
| 51 | { 1, 0, -1 }, /* P4: smartcard, no OC */ |
| 52 | { 1, 1, -1 }, /* P5: ExpressCard, no OC */ |
| 53 | { 0, 0, -1 }, /* P6: empty */ |
| 54 | { 0, 0, -1 }, /* P7: empty */ |
| 55 | { 1, 1, 4 }, /* P8: system port 3, OC4*/ |
| 56 | { 1, 1, 5 }, /* P9: system port 1 (EHCI debug), OC 5 */ |
| 57 | { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ |
| 58 | { 1, 0, -1 }, /* P11: bluetooth, no OC. */ |
| 59 | { 1, 1, -1 }, /* P12: docking, no OC */ |
| 60 | { 1, 1, -1 }, /* P13: camera (LCD), no OC */ |
| 61 | }; |
| 62 | |
| Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 63 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
| Nicolas Reinecke | 2bffa8a | 2015-10-01 15:34:37 +0200 | [diff] [blame] | 64 | { |
| Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 65 | read_spd(&spd[0], 0x50, id_only); |
| 66 | read_spd(&spd[2], 0x51, id_only); |
| Nicolas Reinecke | 2bffa8a | 2015-10-01 15:34:37 +0200 | [diff] [blame] | 67 | } |
| 68 | |
| 69 | void mainboard_early_init(int s3resume) |
| 70 | { |
| 71 | } |
| 72 | |
| 73 | void mainboard_config_superio(void) |
| 74 | { |
| 75 | } |