| Nicolas Reinecke | 2bffa8a | 2015-10-01 15:34:37 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * Copyright (C) 2014 Vladimir Serbinenko |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #define THINKPAD_EC_GPE 17 |
| 19 | #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB |
| 20 | #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB |
| 21 | #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 |
| 22 | #define EC_LENOVO_H8_ME_WORKAROUND 1 |
| 23 | |
| 24 | DefinitionBlock( |
| 25 | "dsdt.aml", |
| 26 | "DSDT", |
| 27 | 0x02, // DSDT revision: ACPI v2.0 |
| 28 | "COREv4", // OEM id |
| 29 | "COREBOOT", // OEM table id |
| 30 | 0x20110725 // OEM revision |
| 31 | ) |
| 32 | { |
| 33 | #include <southbridge/intel/bd82x6x/acpi/platform.asl> |
| 34 | |
| 35 | // Some generic macros |
| 36 | #include "acpi/platform.asl" |
| 37 | |
| 38 | // global NVS and variables |
| 39 | #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> |
| 40 | |
| 41 | #include <cpu/intel/model_206ax/acpi/cpu.asl> |
| 42 | |
| 43 | Scope (\_SB) { |
| 44 | Device (PCI0) |
| 45 | { |
| 46 | #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> |
| 47 | #include <southbridge/intel/bd82x6x/acpi/pch.asl> |
| 48 | #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> |
| 49 | |
| 50 | #include <drivers/intel/gma/acpi/default_brightness_levels.asl> |
| 51 | } |
| 52 | } |
| 53 | |
| 54 | /* |
| 55 | * LPC Trusted Platform Module |
| 56 | */ |
| 57 | Scope (\_SB.PCI0.LPCB) |
| 58 | { |
| 59 | #include <drivers/pc80/tpm/acpi/tpm.asl> |
| 60 | } |
| 61 | |
| 62 | /* Chipset specific sleep states */ |
| 63 | #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> |
| 64 | } |