blob: 755f176e9177f0d2e71bb4df908381eaf34de371 [file] [log] [blame]
Tobias Diedrichcee930a2017-02-12 14:09:06 +01001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008-2009 coresystems GmbH
5 * Copyright (C) 2014 Vladimir Serbinenko
6 * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; version 2 of
11 * the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include "ec.h"
20
21#include <arch/io.h>
22#include <console/console.h>
23#include <cpu/x86/smm.h>
24#include <delay.h>
25#include <ec/acpi/ec.h>
26#include <ec/compal/ene932/ec.h>
27#include <southbridge/intel/bd82x6x/pch.h>
28
29#define GPE_PALMDET1 2
30#define GPE_PALMDET2 4
31#define GPE_EC_SCI 7
32#define GPE_EC_SMI 8
33/* FIXME: check this */
34#define GPE_EC_WAKE 13
35
36static void mainboard_smm_init(void)
37{
38 printk(BIOS_DEBUG, "initializing SMI\n");
39}
40
41int mainboard_io_trap_handler(int smif)
42{
43 static int smm_initialized;
44
45 if (!smm_initialized) {
46 mainboard_smm_init();
47 smm_initialized = 1;
48 }
49
50 return 0;
51}
52
53enum sleep_states {
54 S0 = 0,
55 S1 = 1,
56 S3 = 3,
57 S4 = 4,
58 S5 = 5,
59};
60
61enum ec_smi_event {
62 EC_SMI_EVENT_IDLE = 0x80,
63 EC_SMI_BATTERY_LOW = 0xb3,
64};
65
66/* Tell EC to operate in APM mode. Events generate SMIs instead of SCIs. */
67static void ec_enter_apm_mode(void)
68{
69 ec_kbc_write_cmd(0x59);
70 ec_kbc_write_ib(0xE9);
71}
72/* Tell EC to operate in ACPI mode, thus generating SCIs on events, not SMIs. */
73static void ec_enter_acpi_mode(void)
74{
75 ec_kbc_write_cmd(0x59);
76 ec_kbc_write_ib(0xE8);
77}
78
79static uint8_t ec_get_smi_event(void)
80{
81 ec_kbc_write_cmd(0x56);
82 return ec_kbc_read_ob();
83}
84
85static void ec_process_smi(uint8_t src)
86{
87 /*
88 * Reading the SMI source satisfies the EC in terms of responding to
89 * the event, regardless of whether we take an action or not.
90 */
91
92 printk(BIOS_DEBUG, "Unhandled EC_SMI event 0x%x\n", src);
93}
94
95static void handle_ec_smi(void)
96{
97 uint8_t src;
98
99 while ((src = ec_get_smi_event()) != EC_SMI_EVENT_IDLE)
100 ec_process_smi(src);
101}
102
103void mainboard_smi_gpi(u32 gpi_sts)
104{
105 if (gpi_sts & (1 << GPE_EC_SMI))
106 handle_ec_smi();
107}
108
109int mainboard_smi_apmc(u8 data)
110{
111 printk(BIOS_INFO, "mainboard_smi_apmc(%02x)\n", data);
112
113 switch (data) {
114 case APM_CNT_ACPI_ENABLE:
115 printk(BIOS_DEBUG, "Enable ACPI mode\n");
116 ec_enter_acpi_mode();
117 gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI);
118 gpi_route_interrupt(GPE_PALMDET1, GPI_IS_SCI);
119 gpi_route_interrupt(GPE_PALMDET2, GPI_IS_SCI);
120 break;
121 case APM_CNT_ACPI_DISABLE:
122 printk(BIOS_DEBUG, "Disable ACPI mode\n");
123 ec_enter_apm_mode();
124 gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI);
125 break;
126 default:
127 printk(BIOS_DEBUG, "Unhandled ACPI command: 0x%x\n", data);
128 }
129 return 0;
130}
131
132void mainboard_smi_sleep(u8 slp_typ)
133{
134 if (slp_typ == S3) {
135 u8 ec_wake = ec_read(0x32);
136 /* If EC wake events are enabled, enable wake on EC WAKE GPE. */
137 if (ec_wake & 0x14)
138 gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI);
139 }
140}