| Patrick Rudolph | aae6e9c | 2016-12-30 17:02:04 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2016 Patrick Rudolph <siro@das-labor.org> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #include <arch/io.h> |
| 19 | #include <device/pci_def.h> |
| 20 | #include <device/pnp_def.h> |
| 21 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 22 | #include <northbridge/intel/sandybridge/raminit_native.h> |
| 23 | #include <southbridge/intel/bd82x6x/pch.h> |
| 24 | #include <southbridge/intel/common/gpio.h> |
| 25 | |
| 26 | void pch_enable_lpc(void) |
| 27 | { |
| 28 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3c0f); |
| 29 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c1611); |
| 30 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00040069); |
| 31 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0701); |
| 32 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); |
| 33 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); |
| 34 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000); |
| 35 | } |
| 36 | |
| 37 | void rcba_config(void) |
| 38 | { |
| 39 | /* Disable devices. */ |
| 40 | RCBA32(0x3414) = 0x00000000; |
| 41 | RCBA32(0x3418) = 0x00000000; |
| 42 | |
| 43 | } |
| 44 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 45 | { 1, 0, -1 }, |
| 46 | { 1, 0, -1 }, |
| 47 | { 1, 0, -1 }, |
| 48 | { 1, 0, -1 }, |
| 49 | { 1, 0, -1 }, |
| 50 | { 1, 0, -1 }, |
| 51 | { 1, 0, -1 }, |
| 52 | { 1, 0, -1 }, |
| 53 | { 1, 0, -1 }, |
| 54 | { 1, 0, -1 }, |
| 55 | { 1, 0, -1 }, |
| 56 | { 1, 0, -1 }, |
| 57 | { 1, 0, -1 }, |
| 58 | { 1, 0, -1 }, |
| 59 | }; |
| 60 | |
| 61 | void mainboard_early_init(int s3resume) |
| 62 | { |
| 63 | } |
| 64 | |
| 65 | void mainboard_config_superio(void) |
| 66 | { |
| 67 | } |
| 68 | |
| 69 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
| 70 | { |
| 71 | read_spd(&spd[0], 0x50, id_only); |
| 72 | read_spd(&spd[2], 0x52, id_only); |
| 73 | } |