| Edward O'Callaghan | 32960e3 | 2014-11-23 17:38:52 +1100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Advanced Micro Devices, Inc. |
| 5 | * Copyright (C) 2013 Sage Electronic Engineering, LLC |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| Edward O'Callaghan | 32960e3 | 2014-11-23 17:38:52 +1100 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include "mainboard.h" |
| 18 | |
| 19 | /* DefinitionBlock Statement */ |
| 20 | DefinitionBlock ( |
| 21 | "DSDT.AML", /* Output filename */ |
| 22 | "DSDT", /* Signature */ |
| 23 | 0x02, /* DSDT Revision, needs to be 2 for 64bit */ |
| 24 | "AMD ", /* OEMID */ |
| 25 | "COREBOOT", /* TABLE ID */ |
| 26 | 0x00010001 /* OEM Revision */ |
| 27 | ) |
| 28 | { /* Start of ASL file */ |
| 29 | /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ |
| 30 | |
| 31 | /* Globals for the platform */ |
| 32 | #include "acpi/mainboard.asl" |
| 33 | |
| 34 | /* Describe the USB Overcurrent pins */ |
| 35 | #include "acpi/usb_oc.asl" |
| 36 | |
| 37 | /* PCI IRQ mapping for the Southbridge */ |
| 38 | #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> |
| 39 | |
| 40 | /* Describe the processor tree (\_PR) */ |
| 41 | #include <cpu/amd/agesa/family15rl/acpi/cpu.asl> |
| 42 | |
| 43 | /* Describe the supported Sleep States for this Southbridge */ |
| 44 | #include <southbridge/amd/agesa/hudson/acpi/sleepstates.asl> |
| 45 | |
| 46 | /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */ |
| 47 | #include "acpi/sleep.asl" |
| 48 | |
| 49 | Scope(\_SB) { |
| 50 | /* global utility methods expected within the \_SB scope */ |
| 51 | #include <arch/x86/acpi/globutil.asl> |
| 52 | |
| 53 | /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ |
| 54 | #include "acpi/routing.asl" |
| 55 | |
| 56 | Device(PCI0) { |
| 57 | /* Describe the AMD Northbridge */ |
| 58 | #include <northbridge/amd/agesa/family15rl/acpi/northbridge.asl> |
| 59 | |
| 60 | /* Describe the AMD Fusion Controller Hub Southbridge */ |
| 61 | #include <southbridge/amd/agesa/hudson/acpi/fch.asl> |
| 62 | |
| 63 | } |
| 64 | |
| 65 | /* Describe PCI INT[A-H] for the Southbridge */ |
| 66 | #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl> |
| 67 | |
| 68 | } /* End Scope(_SB) */ |
| 69 | |
| 70 | Scope(\_SB.PCI0.LIBR) { |
| 71 | #include "acpi/ec.asl" |
| 72 | } |
| 73 | |
| 74 | /* Describe SMBUS for the Southbridge */ |
| 75 | #include <southbridge/amd/agesa/hudson/acpi/smbus.asl> |
| 76 | |
| 77 | /* Define the General Purpose Events for the platform */ |
| 78 | #include "acpi/gpe.asl" |
| 79 | |
| 80 | /* Define the Thermal zones and methods for the platform */ |
| 81 | #include "acpi/thermal.asl" |
| 82 | |
| 83 | /* Define the System Indicators for the platform */ |
| 84 | #include "acpi/si.asl" |
| 85 | |
| 86 | } |
| 87 | /* End of ASL file */ |