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review.coreboot.org / coreboot / a50ced2eba20a007fa5b486c251c252ad09868cf / . / src / mainboard / lenovo / g505s / acpi / routing.asl
blob: 22c45501a6025ef3b58b212368930875c0f346c0 [file] [log] [blame]
Edward O'Callaghan32960e32014-11-23 17:38:52 +1100[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 * Copyright (C) 2013 Sage Electronic Engineering, LLC
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Edward O'Callaghan32960e32014-11-23 17:38:52 +1100[diff] [blame]15 */
16
17 /* Routing is in System Bus scope */
18 Name(PR0, Package(){
19 /* NB devices */
20 /* Bus 0, Dev 0 - F15 Host Controller */
Edward O'Callaghan14581fc62014-12-05 04:25:44 +1100[diff] [blame]21 Package(){0x0000FFFF, 0, INTA, 0 },
22 Package(){0x0000FFFF, 1, INTB, 0 },
23 Package(){0x0000FFFF, 2, INTC, 0 },
24 Package(){0x0000FFFF, 3, INTD, 0 },
25
Edward O'Callaghan32960e32014-11-23 17:38:52 +1100[diff] [blame]26 /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
27 Package(){0x0001FFFF, 0, INTB, 0 },
28 Package(){0x0001FFFF, 1, INTC, 0 },
29
30 /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
31 Package(){0x0002FFFF, 0, INTC, 0 },
32 Package(){0x0002FFFF, 1, INTD, 0 },
33 Package(){0x0002FFFF, 2, INTA, 0 },
34 Package(){0x0002FFFF, 3, INTB, 0 },
35
36 /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
37 Package(){0x0003FFFF, 0, INTD, 0 },
38 Package(){0x0003FFFF, 1, INTA, 0 },
39 Package(){0x0003FFFF, 2, INTB, 0 },
40 Package(){0x0003FFFF, 3, INTC, 0 },
41
42 /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
43 Package(){0x0004FFFF, 0, INTA, 0 },
44 Package(){0x0004FFFF, 1, INTB, 0 },
45 Package(){0x0004FFFF, 2, INTC, 0 },
46 Package(){0x0004FFFF, 3, INTD, 0 },
47
48 /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
49 Package(){0x0005FFFF, 0, INTB, 0 },
50 Package(){0x0005FFFF, 1, INTC, 0 },
51 Package(){0x0005FFFF, 2, INTD, 0 },
52 Package(){0x0005FFFF, 3, INTA, 0 },
53
54 /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
55 Package(){0x0006FFFF, 0, INTC, 0 },
56 Package(){0x0006FFFF, 1, INTD, 0 },
57 Package(){0x0006FFFF, 2, INTA, 0 },
58 Package(){0x0006FFFF, 3, INTB, 0 },
59
60 /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
61 Package(){0x0007FFFF, 0, INTD, 0 },
62 Package(){0x0007FFFF, 1, INTA, 0 },
63 Package(){0x0007FFFF, 2, INTB, 0 },
64 Package(){0x0007FFFF, 3, INTC, 0 },
65
66 /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
67
68 /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
69 Package(){0x0014FFFF, 0, INTA, 0 },
70 Package(){0x0014FFFF, 1, INTB, 0 },
71 Package(){0x0014FFFF, 2, INTC, 0 },
72 Package(){0x0014FFFF, 3, INTD, 0 },
73
74 /* SB devices */
75 /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
76 * EHCI @ func 2 */
77 Package(){0x0012FFFF, 0, INTC, 0 },
78 Package(){0x0012FFFF, 1, INTB, 0 },
79
80 Package(){0x0013FFFF, 0, INTC, 0 },
81 Package(){0x0013FFFF, 1, INTB, 0 },
82
83 Package(){0x0016FFFF, 0, INTC, 0 },
84 Package(){0x0016FFFF, 1, INTB, 0 },
85
86 /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
87 Package(){0x0010FFFF, 0, INTC, 0 },
88 Package(){0x0010FFFF, 1, INTB, 0 },
89
90 /* Bus 0, Dev 17 - SATA controller */
91 Package(){0x0011FFFF, 0, INTD, 0 },
92
93 /* Bus 0, Dev 21 Pcie Bridge */
94 Package(){0x0015FFFF, 0, INTA, 0 },
95 Package(){0x0015FFFF, 1, INTB, 0 },
96 Package(){0x0015FFFF, 2, INTC, 0 },
97 Package(){0x0015FFFF, 3, INTD, 0 },
98 })
99
100 Name(APR0, Package(){
101 /* NB devices in APIC mode */
102 /* Bus 0, Dev 0 - F15 Host Controller */
103
104 /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
105 Package(){0x0001FFFF, 0, 0, 17 },
106 Package(){0x0001FFFF, 1, 0, 18 },
107
108 /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
109 Package(){0x0002FFFF, 0, 0, 18 },
110 Package(){0x0002FFFF, 1, 0, 19 },
111 Package(){0x0002FFFF, 2, 0, 16 },
112 Package(){0x0002FFFF, 3, 0, 17 },
113
114 /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
115 Package(){0x0003FFFF, 0, 0, 19 },
116 Package(){0x0003FFFF, 1, 0, 16 },
117 Package(){0x0003FFFF, 2, 0, 17 },
118 Package(){0x0003FFFF, 3, 0, 18 },
119
120 /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
121 Package(){0x0004FFFF, 0, 0, 16 },
122 Package(){0x0004FFFF, 1, 0, 17 },
123 Package(){0x0004FFFF, 2, 0, 18 },
124 Package(){0x0004FFFF, 3, 0, 19 },
125
126 /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
127 Package(){0x0005FFFF, 0, 0, 17 },
128 Package(){0x0005FFFF, 1, 0, 18 },
129 Package(){0x0005FFFF, 2, 0, 19 },
130 Package(){0x0005FFFF, 3, 0, 16 },
131
132 /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
133 Package(){0x0006FFFF, 0, 0, 18 },
134 Package(){0x0006FFFF, 1, 0, 19 },
135 Package(){0x0006FFFF, 2, 0, 16 },
136 Package(){0x0006FFFF, 3, 0, 17 },
137
138 /* Bus 0, Dev 7 - PCIe Bridge for network card */
139 Package(){0x0007FFFF, 0, 0, 19 },
140 Package(){0x0007FFFF, 1, 0, 16 },
141 Package(){0x0007FFFF, 2, 0, 17 },
142 Package(){0x0007FFFF, 3, 0, 18 },
143
144 /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
145
146 /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
147 Package(){0x0014FFFF, 0, 0, 16 },
148 Package(){0x0014FFFF, 1, 0, 17 },
149 Package(){0x0014FFFF, 2, 0, 18 },
150 Package(){0x0014FFFF, 3, 0, 19 },
151
152 /* SB devices in APIC mode */
153 /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
154 * EHCI @ func 2 */
155 Package(){0x0012FFFF, 0, 0, 18 },
156 Package(){0x0012FFFF, 1, 0, 17 },
157
158 Package(){0x0013FFFF, 0, 0, 18 },
159 Package(){0x0013FFFF, 1, 0, 17 },
160
161 Package(){0x0016FFFF, 0, 0, 18 },
162 Package(){0x0016FFFF, 1, 0, 17 },
163
164 /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
165 Package(){0x0010FFFF, 0, 0, 0x12},
166 Package(){0x0010FFFF, 1, 0, 0x11},
167
168 /* Bus 0, Dev 17 - SATA controller */
169 Package(){0x0011FFFF, 0, 0, 19 },
170
171 /* Bus0, Dev 21 PCIE Bridge */
172 Package(){0x0015FFFF, 0, 0, 16 },
173 Package(){0x0015FFFF, 1, 0, 17 },
174 Package(){0x0015FFFF, 2, 0, 18 },
175 Package(){0x0015FFFF, 3, 0, 19 },
176 })
177
178 Name(PS2, Package(){
179 /* The external GFX - Hooked to PCIe slot 2 */
180 Package(){0x0000FFFF, 0, INTC, 0 },
181 Package(){0x0000FFFF, 1, INTD, 0 },
182 Package(){0x0000FFFF, 2, INTA, 0 },
183 Package(){0x0000FFFF, 3, INTB, 0 },
184 })
185 Name(APS2, Package(){
186 /* The external GFX - Hooked to PCIe slot 2 */
187 Package(){0x0000FFFF, 0, 0, 18 },
188 Package(){0x0000FFFF, 1, 0, 19 },
189 Package(){0x0000FFFF, 2, 0, 16 },
190 Package(){0x0000FFFF, 3, 0, 17 },
191 })
192
193 Name(PS4, Package(){
194 /* PCIe slot - Hooked to PCIe slot 4 */
195 Package(){0x0000FFFF, 0, INTA, 0 },
196 Package(){0x0000FFFF, 1, INTB, 0 },
197 Package(){0x0000FFFF, 2, INTC, 0 },
198 Package(){0x0000FFFF, 3, INTD, 0 },
199 })
200 Name(APS4, Package(){
201 /* PCIe slot - Hooked to PCIe slot 4 */
202 Package(){0x0000FFFF, 0, 0, 16 },
203 Package(){0x0000FFFF, 1, 0, 17 },
204 Package(){0x0000FFFF, 2, 0, 18 },
205 Package(){0x0000FFFF, 3, 0, 19 },
206 })
207
208 Name(PS5, Package(){
209 /* PCIe slot - Hooked to PCIe slot 5 */
210 Package(){0x0000FFFF, 0, INTB, 0 },
211 Package(){0x0000FFFF, 1, INTC, 0 },
212 Package(){0x0000FFFF, 2, INTD, 0 },
213 Package(){0x0000FFFF, 3, INTA, 0 },
214 })
215 Name(APS5, Package(){
216 /* PCIe slot - Hooked to PCIe slot 5 */
217 Package(){0x0000FFFF, 0, 0, 17 },
218 Package(){0x0000FFFF, 1, 0, 18 },
219 Package(){0x0000FFFF, 2, 0, 19 },
220 Package(){0x0000FFFF, 3, 0, 16 },
221 })
222
223 Name(PS6, Package(){
224 /* PCIe slot - Hooked to PCIe slot 6 */
225 Package(){0x0000FFFF, 0, INTC, 0 },
226 Package(){0x0000FFFF, 1, INTD, 0 },
227 Package(){0x0000FFFF, 2, INTA, 0 },
228 Package(){0x0000FFFF, 3, INTB, 0 },
229 })
230 Name(APS6, Package(){
231 /* PCIe slot - Hooked to PCIe slot 6 */
232 Package(){0x0000FFFF, 0, 0, 18 },
233 Package(){0x0000FFFF, 1, 0, 19 },
234 Package(){0x0000FFFF, 2, 0, 16 },
235 Package(){0x0000FFFF, 3, 0, 17 },
236 })
237
238 Name(PS7, Package(){
239 /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/
240 Package(){0x0000FFFF, 0, INTD, 0 },
241 Package(){0x0000FFFF, 1, INTA, 0 },
242 Package(){0x0000FFFF, 2, INTB, 0 },
243 Package(){0x0000FFFF, 3, INTC, 0 },
244 })
245 Name(APS7, Package(){
246 /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/
247 Package(){0x0000FFFF, 0, 0, 19 },
248 Package(){0x0000FFFF, 1, 0, 16 },
249 Package(){0x0000FFFF, 2, 0, 17 },
250 Package(){0x0000FFFF, 3, 0, 18 },
251 })
252
253 Name(PE0, Package(){
254 /* PCIe slot - Hooked to PCIe Bridge 0*/
255 Package(){0x0000FFFF, 0, INTA, 0 },
256 Package(){0x0000FFFF, 1, INTB, 0 },
257 Package(){0x0000FFFF, 2, INTC, 0 },
258 Package(){0x0000FFFF, 3, INTD, 0 },
259 })
260 Name(APE0, Package(){
261 /* PCIe slot - Hooked to PCIe Bridge 0*/
262 Package(){0x0000FFFF, 0, 0, 16 },
263 Package(){0x0000FFFF, 1, 0, 17 },
264 Package(){0x0000FFFF, 2, 0, 18 },
265 Package(){0x0000FFFF, 3, 0, 19 },
266 })
267
268 Name(PE1, Package(){
269 /* PCIe slot - Hooked to PCIe Bridge 1*/
270 Package(){0x0000FFFF, 0, INTB, 0 },
271 Package(){0x0000FFFF, 1, INTC, 0 },
272 Package(){0x0000FFFF, 2, INTD, 0 },
273 Package(){0x0000FFFF, 3, INTA, 0 },
274 })
275 Name(APE1, Package(){
276 /* PCIe slot - Hooked to PCIe Bridge 1*/
277 Package(){0x0000FFFF, 0, 0, 17 },
278 Package(){0x0000FFFF, 1, 0, 18 },
279 Package(){0x0000FFFF, 2, 0, 19 },
280 Package(){0x0000FFFF, 3, 0, 16 },
281 })
282
283 Name(PE2, Package(){
284 /* PCIe slot - Hooked to PCIe Bridge 2*/
285 Package(){0x0000FFFF, 0, INTC, 0 },
286 Package(){0x0000FFFF, 1, INTD, 0 },
287 Package(){0x0000FFFF, 2, INTA, 0 },
288 Package(){0x0000FFFF, 3, INTB, 0 },
289 })
290 Name(APE2, Package(){
291 /* PCIe slot - Hooked to PCIe Bridge 2*/
292 Package(){0x0000FFFF, 0, 0, 18 },
293 Package(){0x0000FFFF, 1, 0, 19 },
294 Package(){0x0000FFFF, 2, 0, 16 },
295 Package(){0x0000FFFF, 3, 0, 17 },
296 })
297
298 Name(PE3, Package(){
299 /* PCIe slot - Hooked to PCIe Bridge 3 */
300 Package(){0x0000FFFF, 0, INTD, 0 },
301 Package(){0x0000FFFF, 1, INTA, 0 },
302 Package(){0x0000FFFF, 2, INTB, 0 },
303 Package(){0x0000FFFF, 3, INTC, 0 },
304 })
305 Name(APE3, Package(){
306 /* PCIe slot - Hooked to PCIe Bridge 3*/
307 Package(){0x0000FFFF, 0, 0, 19 },
308 Package(){0x0000FFFF, 1, 0, 16 },
309 Package(){0x0000FFFF, 2, 0, 17 },
310 Package(){0x0000FFFF, 3, 0, 18 },
311 })
312
313 /* SB PCI Bridge J21, J22 */
314 Name(PCIB, Package(){
315 /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
316 Package(){0x0005FFFF, 0, 0, 0x14 },
317 Package(){0x0005FFFF, 1, 0, 0x15 },
318 Package(){0x0005FFFF, 2, 0, 0x16 },
319 Package(){0x0005FFFF, 3, 0, 0x17 },
320
321 Package(){0x0006FFFF, 0, 0, 0x15 },
322 Package(){0x0006FFFF, 1, 0, 0x16 },
323 Package(){0x0006FFFF, 2, 0, 0x17 },
324 Package(){0x0006FFFF, 3, 0, 0x14 },
325 })