blob: 0f99d9b69881d89ef4892533e4fc187a51f7bfcb [file] [log] [blame]
Martin Roth58562402015-10-11 10:36:26 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
5 * Copyright (C) 2013 Sage Electronic Engineering, LLC.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Martin Roth58562402015-10-11 10:36:26 +020015 */
16
17#include <types.h>
18#include <string.h>
19#include <cbmem.h>
20#include <console/console.h>
21#include <arch/acpi.h>
22#include <arch/ioapic.h>
23#include <arch/acpigen.h>
24#include <arch/smp/mpspec.h>
25#include <device/device.h>
26#include <device/pci.h>
27#include <device/pci_ids.h>
Martin Roth58562402015-10-11 10:36:26 +020028#include <southbridge/intel/fsp_rangeley/nvs.h>
29#include <northbridge/intel/fsp_rangeley/northbridge.h>
30
31static global_nvs_t *gnvs_;
32
33void acpi_create_gnvs(global_nvs_t *gnvs)
34{
35 gnvs_ = gnvs;
36 memset((void *)gnvs, 0, sizeof(*gnvs));
37 gnvs->apic = 1;
38 gnvs->mpen = 1; /* Enable Multi Processing */
39 gnvs->pcnt = dev_count_cpu();
40
41 /* Enable USB ports in S3 */
42 gnvs->s3u0 = 1;
43 gnvs->s3u1 = 1;
44
45 /*
46 * Enable Front USB ports in S5 by default
47 * to be consistent with back port behavior
48 */
49 gnvs->s5u0 = 1;
50 gnvs->s5u1 = 1;
51
52 /* IGD Displays */
53 gnvs->ndid = 3;
54 gnvs->did[0] = 0x80000100;
55 gnvs->did[1] = 0x80000240;
56 gnvs->did[2] = 0x80000410;
57 gnvs->did[3] = 0x80000410;
58 gnvs->did[4] = 0x00000005;
59
60}
61
62unsigned long acpi_fill_madt(unsigned long current)
63{
64 /* Local APICs */
65 current = acpi_create_madt_lapics(current);
66
67 /* IOAPIC */
68 current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
69 2, IO_APIC_ADDR, 0);
70
71 /* INT_SRC_OVR */
72 current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
73 current, 0, 0, 2, 0);
74 current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
75 current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
76
77 return current;
78}