blob: 27041228f02f0de087ccec295bbc634feb553439 [file] [log] [blame]
Marcin Wojciechowski9586dc72015-11-20 14:53:46 +01001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2007-2008 coresystems GmbH
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
15
16# -----------------------------------------------------------------
17entries
18
19# -----------------------------------------------------------------
20# Status Register A
21# -----------------------------------------------------------------
22# Status Register B
23# -----------------------------------------------------------------
24# Status Register C
25#96 4 r 0 status_c_rsvd
26#100 1 r 0 uf_flag
27#101 1 r 0 af_flag
28#102 1 r 0 pf_flag
29#103 1 r 0 irqf_flag
30# -----------------------------------------------------------------
31# Status Register D
32#104 7 r 0 status_d_rsvd
33#111 1 r 0 valid_cmos_ram
34# -----------------------------------------------------------------
35# Diagnostic Status Register
36#112 8 r 0 diag_rsvd1
37
38# -----------------------------------------------------------------
390 120 r 0 reserved_memory
40#120 264 r 0 unused
41
42# -----------------------------------------------------------------
43# RTC_BOOT_BYTE (coreboot hardcoded)
44384 1 e 4 boot_option
Nico Huberd23ee5d2016-08-11 22:45:55 +020045388 4 h 0 reboot_counter
Marcin Wojciechowski9586dc72015-11-20 14:53:46 +010046#390 2 r 0 unused?
47
48# -----------------------------------------------------------------
49# coreboot config options: console
50392 3 e 5 baud_rate
51395 4 e 6 debug_level
52#399 1 r 0 unused
53
54# coreboot config options: cpu
55400 1 e 2 hyper_threading
56#401 7 r 0 unused
57
58# coreboot config options: southbridge
59408 1 e 1 nmi
60409 2 e 7 power_on_after_fail
61#411 5 r 0 unused
62
63# MRC Scrambler Seed values
64896 32 r 0 mrc_scrambler_seed
65928 32 r 0 mrc_scrambler_seed_s3
66
67# coreboot config options: check sums
68984 16 h 0 check_sum
69#1000 24 r 0 amd_reserved
70
71#save timestamps in pre-ram boot areas
721719 64 h 0 timestamp_value1
731783 64 h 0 timestamp_value2
741847 64 h 0 timestamp_value3
751911 64 h 0 timestamp_value4
761975 64 h 0 timestamp_value5
77
78# -----------------------------------------------------------------
79
80enumerations
81
82#ID value text
831 0 Disable
841 1 Enable
852 0 Enable
862 1 Disable
874 0 Fallback
884 1 Normal
895 0 115200
905 1 57600
915 2 38400
925 3 19200
935 4 9600
945 5 4800
955 6 2400
965 7 1200
976 1 Emergency
986 2 Alert
996 3 Critical
1006 4 Error
1016 5 Warning
1026 6 Notice
1036 7 Info
1046 8 Debug
1056 9 Spew
1067 0 Disable
1077 1 Enable
1087 2 Keep
109# -----------------------------------------------------------------
110checksums
111
112checksum 392 415 984