blob: 857390edccd261a5737812f45435b83205ba98d6 [file] [log] [blame]
Lee Leahy274d20a2016-05-15 13:52:36 -07001/*
2 * This file is part of the coreboot project.
3 *
Lee Leahy0de5b092017-03-06 09:05:41 -08004 * Copyright (C) 2016-2017 Intel Corp.
Lee Leahy274d20a2016-05-15 13:52:36 -07005 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <arch/io.h>
17#include <console/console.h>
Lee Leahy102f6252016-07-25 07:41:54 -070018#include <soc/car.h>
Lee Leahy274d20a2016-05-15 13:52:36 -070019#include <soc/ramstage.h>
Lee Leahy15843bd2016-05-15 15:05:56 -070020#include "reg_access.h"
Lee Leahy274d20a2016-05-15 13:52:36 -070021#include "gen1.h"
22#include "gen2.h"
23
Lee Leahybc518d52016-05-30 15:01:06 -070024void car_mainboard_pre_console_init(void)
25{
26 const struct reg_script *script;
27
28 /* Initialize the GPIO controllers */
29 if (IS_ENABLED(CONFIG_GALILEO_GEN2))
30 script = gen2_gpio_init;
31 else
32 script = gen1_gpio_init;
33 reg_script_run(script);
34
35 /* Initialize the RXD and TXD paths for UART0 */
36 if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0)) {
37 if (IS_ENABLED(CONFIG_GALILEO_GEN2))
38 script = gen2_hsuart0;
39 else
Lee Leahy102f6252016-07-25 07:41:54 -070040 script = (reg_legacy_gpio_read(
41 R_QNC_GPIO_RGLVL_RESUME_WELL)
Lee Leahybc518d52016-05-30 15:01:06 -070042 & GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO)
Lee Leahy5d94c262016-06-18 09:54:43 -070043 ? gen1_hsuart0_0x20 : gen1_hsuart0_0x21;
Lee Leahybc518d52016-05-30 15:01:06 -070044 reg_script_run(script);
45 }
46}
47
Lee Leahy15843bd2016-05-15 15:05:56 -070048void mainboard_gpio_i2c_init(device_t dev)
49{
50 const struct reg_script *script;
51
52 printk(BIOS_INFO, "Galileo I2C chip initialization\n");
53
54 /* Determine the correct script for the board */
55 if (IS_ENABLED(CONFIG_GALILEO_GEN2))
56 script = gen2_i2c_init;
57 else
58 /* Determine which I2C address is in use */
Lee Leahy0de5b092017-03-06 09:05:41 -080059 script = (reg_legacy_gpio_read(R_QNC_GPIO_RGLVL_RESUME_WELL)
Lee Leahy15843bd2016-05-15 15:05:56 -070060 & GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO)
Lee Leahy5d94c262016-06-18 09:54:43 -070061 ? gen1_i2c_0x20_init : gen1_i2c_0x21_init;
Lee Leahy15843bd2016-05-15 15:05:56 -070062
63 /* Initialize the I2C chips */
64 reg_script_run(script);
65}
66
Lee Leahy5ef051a2016-04-29 15:16:54 -070067void mainboard_gpio_pcie_reset(uint32_t pin_value)
68{
69 uint32_t pin_number;
70 uint32_t value;
71
72 /* Determine the correct PCIe reset pin */
73 if (IS_ENABLED(CONFIG_GALILEO_GEN2))
74 pin_number = GEN2_PCI_RESET_RESUMEWELL_GPIO;
75 else
76 pin_number = GEN1_PCI_RESET_RESUMEWELL_GPIO;
77
78 /* Update the PCIe reset value */
79 value = reg_legacy_gpio_read(R_QNC_GPIO_RGLVL_RESUME_WELL);
80 value = (value & ~(1 << pin_number)) | ((pin_value & 1) << pin_number);
81 reg_legacy_gpio_write(R_QNC_GPIO_RGLVL_RESUME_WELL, value);
82}