blob: f7d666d6f51e381b18c9a652108b49c2dbf51cf1 [file] [log] [blame]
Lee Leahy93dd5f72016-01-26 10:06:42 -08001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2013 Google Inc.
5## Copyright (C) 2015-2016 Intel Corp.
6##
7## This program is free software; you can redistribute it and/or modify
8## it under the terms of the GNU General Public License as published by
9## the Free Software Foundation; version 2 of the License.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
16
17chip soc/intel/quark
18
Lee Leahyd76d60b2016-03-03 15:30:48 -080019 ############################################################
20 # Set the parameters for MemoryInit
21 ############################################################
22
Lee Leahydc542702016-06-18 18:52:43 -070023 register "AddrMode" = "0"
24 register "ChanMask" = "1" # Channel 0 enabled
25 register "ChanWidth" = "1" # 16-bit channel
26 register "DramDensity" = "1" # 1 Gib;
27 register "DramRonVal" = "0" # 34 Ohm
28 register "DramRttNomVal" = "2" # 120 Ohm
29 register "DramRttWrVal" = "0" # off
30 register "DramSpeed" = "0" # 800 MHz
31 register "DramType" = "0" # DDR3
32 register "DramWidth" = "0" # 8-bit
33 register "EccScrubBlkSize" = "2" # 64 byte blocks
34 register "EccScrubInterval" = "0" # ECC scrub disabled
35 register "Flags" = "MRC_FLAG_SCRAMBLE_EN"
36 register "FspReservedMemoryLength" = "0x00100000" # Size in bytes
37 register "RankMask" = "1" # RANK 0 enabled
38 register "SmmTsegSize" = "0" # SMM Region size in MiB
39 register "SocRdOdtVal" = "0" # off
40 register "SocWrRonVal" = "1" # 32 Ohm
41 register "SocWrSlewRate" = "1" # 4V/nSec
42 register "SrInt" = "3" # 7.8 uSec
43 register "SrTemp" = "0" # normal
44 register "tCL" = "6" # clocks
45 register "tFAW" = "40000" # picoseconds
46 register "tRAS" = "37500" # picoseconds
47 register "tRRD" = "10000" # picoseconds
48 register "tWTR" = "10000" # picoseconds
Lee Leahyd76d60b2016-03-03 15:30:48 -080049
50 ############################################################
51 # Enable the devices
52 ############################################################
53
Lee Leahy93dd5f72016-01-26 10:06:42 -080054 device domain 0 on
55 # EDS Table 3
Lee Leahy7fcaf772016-02-14 15:18:14 -080056 device pci 00.0 on end # 8086 0958 - Host Bridge
Lee Leahy6d3cd082016-02-29 08:03:53 -080057 device pci 14.0 on end # 8086 08A7 - SD/SDIO/eMMC controller
Lee Leahy7fcaf772016-02-14 15:18:14 -080058 device pci 14.1 off end # 8086 0936 - HSUART 0
Lee Leahy27727932016-05-22 10:07:20 -070059 device pci 14.2 on end # 8086 0939 - USB 2.0 Device port
Lee Leahya9a06ee2016-02-28 11:35:29 -080060 device pci 14.3 on end # 8086 0939 - USB EHCI Host controller
61 device pci 14.4 on end # 8086 093A - USB OHCI Host controller
Lee Leahy654fd072016-02-17 08:47:58 -080062 device pci 14.5 on end # 8086 0936 - HSUART 1
Lee Leahy7fcaf772016-02-14 15:18:14 -080063 device pci 14.6 off end # 8086 0937 - 10/100 Ethernet MAC 0
64 device pci 14.7 off end # 8086 0937 - 10/100 Ethernet MAC 1
Lee Leahy1f1f2c42016-03-03 15:30:48 -080065 device pci 15.0 on end # 8086 0935 - SPI controller 0
66 device pci 15.1 on end # 8086 0935 - SPI controller 1
Lee Leahyb1900792016-04-30 09:07:14 -070067 device pci 15.2 on end # 8086 0934 - I2C/GPIO controller
Lee Leahy18452622016-02-16 08:26:03 -080068 device pci 17.0 on end # 8086 11C3 - PCIe Root Port 0
Lee Leahy7fcaf772016-02-14 15:18:14 -080069 device pci 17.1 off end # 8086 11C4 - PCIe Root Port 1
70 device pci 1f.0 on end # 8086 095E - Legacy Bridge
Lee Leahy93dd5f72016-01-26 10:06:42 -080071 end
72end