blob: 0267d629530c75ea59c21be4db6cd9f0a2dce691 [file] [log] [blame]
Thomas Jourdan1a692d82009-07-01 17:01:17 +00001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Thomas Jourdan1a692d82009-07-01 17:01:17 +000015 */
16
17#include <arch/pirq_routing.h>
18
Stefan Reinauera47bd912012-11-15 15:15:15 -080019static const struct irq_routing_table intel_irq_routing_table = {
Thomas Jourdan1a692d82009-07-01 17:01:17 +000020 PIRQ_SIGNATURE, /* u32 signature */
21 PIRQ_VERSION, /* u16 version */
Uwe Hermann95313d82009-10-07 21:51:33 +000022 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
Thomas Jourdan1a692d82009-07-01 17:01:17 +000023 0x00, /* Interrupt router bus */
24 (0x1f << 3) | 0x0, /* Interrupt router dev */
25 0, /* IRQs devoted exclusively to PCI usage */
26 0x8086, /* Vendor */
27 0x2670, /* Device */
28 0, /* Miniport */
29 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
30 0x4b, /* Checksum (has to be set to some value that
31 * would give 0 after the sum of all bytes
32 * for this structure (including checksum).
Elyes HAOUASf4df9d12016-09-23 17:57:38 +020033 */
Thomas Jourdan1a692d82009-07-01 17:01:17 +000034 {
35 /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
36 {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
37 {0x00, (0x02 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0},
38 {0x00, (0x03 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0},
39 {0x00, (0x1f << 3) | 0x0, {{0x00, 0x0000}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
40 {0x00, (0x1d << 3) | 0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
41 {0x00, (0x1c << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0},
42 {0x02, (0x00 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x20, 0x0},
43 {0x01, (0x00 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x1, 0x0},
44 {0x01, (0x01 << 3) | 0x0, {{0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
45 }
46};
47
48unsigned long write_pirq_routing_table(unsigned long addr)
49{
Stefan Reinauera47bd912012-11-15 15:15:15 -080050 return copy_pirq_routing_table(addr, &intel_irq_routing_table);
Thomas Jourdan1a692d82009-07-01 17:01:17 +000051}