blob: cf52c01f0466fd9c58c6353f0c16b29a17250491 [file] [log] [blame]
York Yang9c6c7912016-03-09 11:19:51 -08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google Inc.
5 * Copyright (C) 2015 Intel Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <stddef.h>
18#include <soc/romstage.h>
19#include <drivers/intel/fsp1_0/fsp_util.h>
20
21/**
22 * /brief mainboard call for setup that needs to be done before fsp init
23 *
24 */
25void early_mainboard_romstage_entry(void)
26{
27
28}
29
30/**
31 * /brief mainboard call for setup that needs to be done after fsp init
32 *
33 */
34void late_mainboard_romstage_entry(void)
35{
36
37}
38
39/**
40 * /brief customize fsp parameters here if needed
41 */
42void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
43{
44
45}